[Xilinx Vivado bit,mcs,elf,mcs Make]
1. SDK -> Program FPGA -> download.bit (FPGA bit file + F/W elf merge and make)
2. VIVADO Tcl Console
cd /Project/SFP_JIG/project_4/project_4.sdk/SDK/SDK_Export/hw_platform_0
cd z:/fpga/project_4/project_4.sdk/SDK/SDK_Export/hw_platform_0
-> MCS file Make
3. Program Configuration Memory Device
write_cfgmem -format mcs -interface spix4 -size 64 -loadbit "up 0 ./download.bit" -file main15121616.mcs
C:\Project\SFP_JIG\project_4\project_4.sdk\SDK\SDK_Export\SFP_FW\Debug\SFP_FW.elf
4.
cd /Project/SFP_JIG/project_4/project_4.runs/impl_3
source -quiet write_mmi.tcl
write_mmi lmb_bram
cd /Project/ARTY/project_4/project_4.runs/impl_3
write_bitstream top.bit
data2mem -bm top_bd.bmm -bt top.bit -o ./download.bit -ofmt b
data2mem -bm top_bd.bmm -bt top.bit -bd C:/Project/ARTY/project_4/project_4.sdk/SDK/SDK_Export/hello/Debug/hello.elf tag u_MB_System_wrapper_0_U0_design_1_i_microblaze_1 -o b download.bit -ofmt b
[lwIP apply]
1. bit/mmi/elf generates.
2. In SDK "Launch Shell" run, change directory program_flash
3. 1 tab 2 tab 3 tab, and then bit Merge (FPGA + Bootload) MCS generation (+ elf Mudgee) Fusing completed
[Xilinx ISE14.7 bit,mcs,elf,mcs Make]
1. ISE Design
--> *.bmm and *.bit file
2. SDK Bootloader
--> *.elf
3. SDK Firmware
--> *.srec
4. download.bit file make
1.and 2. After completing
In the SDK environment Xilinx Tools. --> Make download.bit file through the "Program FPGA" menu.
(bistream + bmm + elf Select)
5. MCS for creating Flash Fusing.
3 and 4 after completion
un impact and "Create PROM file" Select.
1) Storage Target: SPI Flash Single FPGA
2) Choose 128M. And select "Add Storage Device"
3) FF
4) "Output File Name" input
5) Add Device : NO
6) Output File Location Select C:\Project\boot\
6) File Format : MCS
7) Add Non-Configuration Files : Yes
8) Add Data File : Yes
Start Address "60000"
*.srec open
9) ok -> ok -> ok
10) Generate File
6. Fusing MCS creates for Programming should directly after BSCAN.