Timing Closure

http://www.gstitt.ece.ufl.edu/courses/eel4712/lectures/metastability/cdc_wp.pdf

3. Synchronous design techniques

1) One clock : Reliability; faster and easier static timing analysis

2) Use of D-type flip-flops : Reliability; faster and easier static timing analysis

3) One clock edge used to clock data : Reliability; using more than one edge requires a closely controlled duty cycle

4) In place of multiple clocks, use clock enables : Reliability; eliminates clock skew problems; faster and easier static timing analysis

5) Where more than one clock is required, synchronization occurs in one hierarchical block : Minimize problem areas to one location for easier analysis

6) Do NOT create internally derived or divided clocks : Reliability; eliminates clock skew problems and glitching

7) Do not create internal asynchronous sets/resets : Reliability; eliminates glitching that may propagate erroneous data

8) Hierarchy broken into structural blocks defined by functionality : Replicable results that will ease the use of timing constraints; faster and easier timing analysis, debug, portability, use of advanced tools (floorplanning, use of guide files)

9) Leaf-level hierarchical blocks based on the path type (i.e., control, data-path, random logic, etc.) : Synthesis optimization techniques can be used based on the type of logic and the performance objectives of each block; optimization is increased as cores and Xilinx specific coding can be used now, while portability will be easier when targeting newer Xilinx technologies

10) Registered leaf-level outputs for each behavioral hierarchical block. : One of the most important considerations that will greatly ease the application of timing constraints over multiple iterations by preserving hierarchy during synthesis; performance; floorplanning; reducing compilation time; predictable interface timing between leaf-level blocks; easier debug, portability, and application of timing constraints; this implies that you are keeping like-logic together for better optimization; floorplanning techniques can be more easily applied

4. Timing Closure Flow

1. Use proper coding techniques. This includes many topics expanded on below, but primarily

involves the implementation of synchronous design techniques, use of Xilinx specific coding,

and use of cores. In this document, see the following sections:

1) “Code Guidelines”

2) “Synthesis”

3) “Static Timing Analysis”

2. Drive your synthesis tool. Apply period and input/output constraints to drive optimization

results from synthesis. Multi-cycle and false paths can also be applied. Maintain hierarchy to

enable easier debugging in static timing analysis as well as improve your opportunities to

floorplan and to implement incremental or modular design techniques. See the following

sections:

1) “Synthesis”

2) “Static Timing Analysis”

3. Specify wise pin constraints. Pin constraints are often required early in the design cycle so

that board development can begin. Use your knowledge of the FPGA's fabric and the design to

create pin constraints that will take advantage of the FPGA architecture, design flow, and board

requirements. See the following section:

1) “Pin Constraints”

4. Apply global timing constraints to the Xilinx implementation tools. If you meet your

performance objectives, you are finished. If you do not, you can later apply path-specific

timing constraints. Implement the design. See the following sections:

1) “Timing Constraints”

2) “Static Timing Analysis”

5. Verify that your timing objectives are reasonable. Check the logic-level delays of your

critical paths in the Post-Map Timing Report or the Post- Place-and-Route Static Timing

Report. Identify how much of your timing budget is logic delay versus routing delay. Use the

60/40 rule: 60% logic (maximum), leaving 40% (or more) of your timing budget for routing

delays. See the following sections:

1) “Code Guidelines”

2) “Static Timing Analysis”

6. Change the implementation effort level. A higher effort level may meet timing constraints

without having to apply advanced timing constraints, use advanced tools, or change the code.

Implement the design. See the following sections:

1) “Implementation Options”

2) “Static Timing Analysis”

7. Apply path-specific timing constraints. That is, apply multi-cycle, false path, and critical

path constraints to help the implementation tools prioritize the placement and routing of paths.

This can be an iterative process. Start by identifying the multi-cycle paths and false paths. If

there are still paths that fail, constrain the critical paths with the use of a From:To constraint to

give it a higher priority. Implement the design. See the following sections:

1) “Timing Constraints”

2) “Static Timing Analysis”

8. Review the code. At this point, you may find that you can save iteration time by making

certain that your code is fully optimized. By using the timing analysis report generated by

Xilinx, you may be able to identify paths in your code that are not fully optimized. Implement

the design. See the following sections:

1) “Code Guidelines”

2) “Static Timing Analysis”

9. Apply critical path timing constraints for synthesis. This can be an iterative process by

which you identify critical paths to the synthesis tools so that it can work harder and try

different algorithms to reduce the delay on critical paths. Implement the design. See the

following sections:

1) “Synthesis”

2) “Static Timing Analysis”

10. Use the Map -timing option or the Multi-Pass Place-and-Route tool. The Map -timing

option performs a portion of the mapping and place and route process on critical paths in the

design. This can be very useful option for meeting timing constraints on a non-floorplanned

design. If using the Map -timing options does not work, you can next try using Multi-Pass

Place-and-Route. This tool can be very beneficial in finding a placement that will meet or come

close to meeting your performance objectives. Implement the design. See the following

sections:

1) “Static Timing Analysis”

2) “Implementation Options”

11. Floorplan your design. Use the Xilinx Floorplanner tool, PACE, or a third-party physical

synthesis tool to meet your timing objectives. The idea behind using these tools is to specify

locations on the die that the logic be placed, effectively guiding the place and route tools on

placing logic. However, you can also make your timing worse since the tools cannot override

your placement constraints. Implement the design. See the following sections:

1) “Synthesis”

2) “Static Timing Analysis”

3) “Floorplanning”

http://www.xilinx.com/support/documentation/white_papers/wp331.pdf

5. Timing Constraints : Offset

6. Timing Constraints : DCM or PLL

7. Path Trace

7. Timing Report 'Zero'