Embedded Files
Verdi VHDL/Verilog Rule Check
1. Flow
- ls 1_SRC/*.vhd > hdl.list
; Complie List Make
; alias “lntlist”
- vhdlcom -f hdl.list -2000 -smartorder
(vhdlcom -f hdl.list -2000 -smartorder -onfatalerrorcontinue)
;Project VHDL File Comple
;alias “lntcom”
- nLint -gui -top rrh_cpri &
;nLint Execution
;alias “lnt”
- vi vhdlcomLog/compiler.log
;log Analyzer
;alias “lntlog”
2.Verdi Clock Domain Check
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