Verification

1. Verification Using Text File Vector

[example]

integer file, i, code;

reg [9:0] a, b;

initial begin : file_block

a = 10'h3FF;

b = 10'h3FF;

file = $fopen("tb.txt", "r" );

for (i = 0; i < 100; i=i+1) begin

@(posedge clock) // Read stimulus on rising clock

code = $fscanf(file, "%b %b\n", a[9:0], b[9:0]);

end // for

end // initial

2. Timing closure

3. Verification to use chipscope.

4. Verification to use test-program.

5. Verification to use MATLAB.

6. Verification to use Signal Integrity

7. Critical Signal temperature test.

8. Verification using the checklist.

10. Using the CPU emulation test-bench.

The necessary files.

1) CPU Emulation code: Reg_ctrl.vhd

2) to replace the software Script: cmd_example.sim

3) Package: text_pkg.vhd

[cmd command usage]

dl 1 us <- Delay 1us

pr RET Test paattern Enable <- Print "RET Test paattern Enable"

ms 90006068 0001 50 ns <- Memory Set(Address Write) ; address 90006068, data 0001, 50ns keep.

md a0200000 1 ns <- Memory Dump(Address Read) ; address a0200000 read, 1ns keep.