Vim

1. Vim basic form

2. Function Key Setting

map <F2> :!ctags -R *.vhd<CR>

map <F3> :TlistToggle<CR>

map <F4> :20vs ./ <CR>

"tab

"map <F5> :tabnew<CR>

map <F5> :browse tabnew ./<CR>

map <C-h> gT

map <C-l> gt

"Comment

map <F6> :s/^/\--<CR>:noh<CR>

map <C-F6> :s/\-\-<CR>:noh<CR>

"folding

map <F7> zf

map <C-F7> zd

"making

map <F8> ma

map <C-F8> 'a

map <F9> : sp<CR>

map <C-F9> : vsp<CR>

map <F10> <c-W> <c-W>

map <C-F10> <c-W> <c-W>

map <F11> <c-W>3+

map <C-F11> <c-W>3>

map <F12> :close<CR

3. VHDL Hot Key of edit mode

iabbr dw downto

iabbr si signal

iabbr gen generate

iabbr ot (others => '0');

iabbr st std_logic;

iabbr sv std_logic_vector(downto 0); <ESC>11ha

iabbr com component COMP_NAME port (<CR> <CR> <Esc>0i);end component;

iabbr pm u_COMP_NAME : COMP_NAME port map (<CR> <CR> <Esc>0i);

iabbr ps process (RESET_N,)<CR>begin<CR>if RESET_N = '0' then<CR>elsif EXAMPLE_CLOCK = '1' and EXAMPLE_CLOCK'event then<CR>end if;<CR>end process;<Esc>?)<CR>i

iabbr ca case is<CR>when STATE1 => ACTION1<CR>when STATE2 => ACTION2<CR>when others => null;<CR>end case;<Esc>4k$2hi

iabbr en <Esc>bdwientity <Esc>pa is<CR>end entity ;<Esc>POport (<CR>);<Esc>O

iabbr ar <Esc>b"zdwiarchitecture <Esc>pa of <Esc>mz?entity<CR>wyw`zpa is<CR>begin<CR>end architecture ;<Esc>"zPO

iabbr li library ieee;<CR>use ieee.std_logic_1164.all;<CR>use ieee.std_logic_signed.all;<CR>use ieee.std_logic_arith.all;<CR> <Esc>bo<Esc>o<Esc>o

4. Automatic Generation

:command! -nargs=1 -complete=file VHDLcomp r! perl ./vhdl/vhdl_comp.pl <args>

:command! -nargs=1 -complete=file VHDLinst r! perl ./vhdl/vhdl_inst.pl <args>

:command! -nargs=1 -complete=file VHDLtb r! perl ./vhdl/vhdl_tb.pl <args>

imap <buffer> <C-s>i <Esc>:VHDLinst

imap <buffer> <C-s>c <Esc>:VHDLcomp

imap <buffer> <C-s>t <Esc>:VHDLtb