1. Array Syntax
[Package Declaration]
type std_logic_array8 is array(natural range <>) of std_logic_vector(7 downto 0);
[Port Declaration]
iHW_WORD_P0 : out std_logic_array8(35 downto 0);
iHW_WORD_P1 : out std_logic_array8(35 downto 0);
oHW_WORD_P0 : in std_logic_array8(35 downto 0);
oHW_WORD_P1 : in std_logic_array8(35 downto 0);
[signal Declaration]
signal iHW_WORD_P0 : std_logic_array8(35 downto 0);
signal oHW_WORD_P0 : std_logic_array8(35 downto 0);
signal iHW_WORD_P1 : std_logic_array8(35 downto 0);
signal oHW_WORD_P1 : std_logic_array8(35 downto 0);
[Mapping]
oHW_WORD0_P0 <= oHW_WORD_P0(0);
…
oHW_WORD35_P3 <= oHW_WORD_P2(35);
iHW_WORD_P0(0) <= iHW_WORD0_P0;
…
iHW_WORD_P2(35) <= iHW_WORD35_P3;
2. Record Syntax
[Package Declaration]
type cpu_in_type16 is
record
CPU_CLK : std_logic;
CS : std_logic;
ADDR : std_logic_vector(7 downto 0);
WEN : std_logic;
REN : std_logic;
DATA_I : std_logic_vector(15 downto 0);
DATA_O : std_logic_vector(15 downto 0);
end record;
[Port Declaration]
F0_CPU_IF : inout cpu_in_type16;
[signal Declaration]
signal F0_CPU_IF : cpu_in_type16;
signal F1_CPU_IF : cpu_in_type16;
[Mapping]
F_DATA_I <= F_CPU_IF.DATA_I;
F_ADDR <= F_CPU_IF.ADDR;
F_WEN <= F_CPU_IF.WEN;
F_REN <= F_CPU_IF.REN;
F_CS <= F_CPU_IF.CS;
F_CPU_CLK <= F_CPU_IF.CPU_CLK;
F_CPU_IF.DATA_O <= register;
3. SPI Testbench
--Procedures
procedure do_spi (signal txdat : inout std_logic_vector(breite-1 downto 0);
SIGNAL SCL : out std_logic;
SIGNAL SDA : out std_logic
)
is
begin
SDA <= '1';
SCL <= '1';
wait for 100 ns;
SCL <= '1';
wait for 100 ns;
SCL <= '0';
SDA <= txdat(txdat'left);
for I in txdat'range loop
wait for 100 ns;
SCL <= '1';
txdat<= txdat(txdat'left-1 downto 0) & '0';
wait for 100 ns;
SCL <= '0';
SDA <= txdat(txdat'left);
end loop;
wait for 200 ns;
wait for 500 ns;
end do_spi;
-- process
tb : PROCESS
BEGIN
txdat <= x"52" & '1' & 'Z' & "ZZZZZZZZ" & 'Z'; --read 52
do_spi(SCL=>SCL,SDA=>SDA,txdat=>txdat);
txdat <= x"52" & '0' & '0' & x"01" & '0'; --write 52 -> 01
do_spi(SCL=>SCL,SDA=>SDA,txdat=>txdat);
txdat <= x"AA" & '0' & '0' & x"55" & '0'; --write AA -> 55
do_spi(SCL=>SCL,SDA=>SDA,txdat=>txdat);
wait;
END PROCESS;
4. Management Process Testbench
[Package Declaration]
procedure read(
addr : in add_typ;
data : out dat_typ;
signal to_mgmnt : out to_mgmnt_typ;
signal frm_mgmnt : in frm_mgmnt_typ);
[Testbench]
read(ETH_TRANSMIT_COUNT, data, to_mgmnt, frm_mgmnt);
tbprint(string'("Number of Ethernet frames transmitted = "
& integer'image(to_integer(unsigned(data)))));
read(ETH_RECEIVE_COUNT, data, to_mgmnt, frm_mgmnt);
tbprint(string'("Number of Ethernet frames received = "
& integer'image(to_integer(unsigned(data)))));
if (data = x"00000000") then
assert false report "** Error