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วงจรตรวจจับสัญญาณ ถ้าสัญญาณ X เป็น 0 0 1 y1 = 0 y0 = 1 และถ้าสัญญาณ X เป็น 011 จะได้ y1 = 1 y0 = 0 นอกนั้นทั้ง y1และ y0 เป็น ‘0’ กำหนดให้วงจรนี้ต้องตรวจจับตลอดเวลา ตามตัวอย่าง Timing diagram
State Diagram
VHDL
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.ALL;
entity seq is
port(CLK: in STD_LOGIC;
x: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(1 downto 0));
end seq;
architecture moore_beh of seq is
type state_type is (s0,s1,s2,s3,s4,s5);
signal state: state_type;
begin
process (clk)
begin
if clk = '0' and clk'event then
case state is
when s0 =>
if x = '0' then
state <= s1;
else
state <= s0;
end if;
when s1 =>
if x = '0' then
state <= s2;
else
state <= s4;
end if;
when s2 =>
if x = '0' then
state <= s2;
else
state <= s3;
end if;
when s3 =>
state <= s0;
when s4 =>
if x = '0' then
state <= s1;
else
state <= s5;
end if;
when s5 =>
state <= s0;
end case;
end if;
end process;
process (state)
begin
case state is
when s0 => y <= "00";
when s1 => y <= "00";
when s2 => y <= "00";
when s3 => y <= "01";
when s4 => y <= "00";
when s5 => y <= "10";
end case;
end process;
end moore_beh;
Testbench
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.ALL;
use IEEE.std_logic_textio.all;
use STD.textio.all;
entity seq_teb is
end seq_teb;
architecture seq_beh of seq_teb is
component seq
port(CLK: in STD_LOGIC;
x: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(1 downto 0));
end component;
signal sclk, sx : std_logic;
signal sy : std_logic_vector(1 downto 0);
begin
DUT: seq port map(CLK => sclk, x => sx, y => sy);
STIMULI: process
variable s_in : line;
variable v_x : std_logic;
variable v_y : std_logic_vector(1 downto 0);
file STIMULI_IN: text is in "seq_vec.txt";
begin
wait for 50 ns;
while not endfile(STIMULI_IN) loop
sclk <= '0';
readline(STIMULI_IN, s_in);
read(s_in,v_x);
read(s_in,v_y);
sx <= v_x;
stmp <= v_y;
wait for 50 ns;
sclk <= '1';
wait for 50 ns;
if v_y /= sy then
assert false
report "circuit failed"
severity Error;
end if;
end loop;
end process STIMULI;
end seq_beh;
Text ไฟล์สำหรับใช้ตรวจสอบ
1 00
1 00
1 00
0 00
0 00
0 00
1 01
1 00
1 00
1 00
1 00
1 00
0 00
1 00
1 10
1 00
0 00
0 00
0 00
1 10
1 00
1 00
0 00
1 00
1 01
1 00
1 00
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