library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PWM_2 is
Port ( clk : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(7 downto 0));
end PWM_2;
architecture Behavioral of PWM_2 is
signal COUNT : integer range 0 to 100 ;
signal sq, sq10 : std_logic;
component DIVIDER is
port (CLK : in std_logic;
Q : out std_logic);
end component;
component DIVIDER10 is
port (CLK: in std_logic;
Q : out std_logic );
end component;
type pw is array(9 downto 1) of integer;
Shared Variable x : pw :=(100,100, 99, 97, 95, 90, 70, 30, 0);
begin
process (sq)
begin
if sq'event and sq = '1' then
if (COUNT >= 100) then
COUNT <= 0;
else
COUNT <= COUNT +1;
end if;
end if;
end process;
process (COUNT)
begin
for i in 0 to 7 loop
if (COUNT >= x(i+1)) then
Q(i) <= '1';
else
Q(i) <= '0';
end if;
end loop;
end process;
process (sq10)
begin
if sq10'event and sq10 = '1' then
x(9) := x(1);
x(7 downto 1) := x(8 downto 2);
x(8) := x(9);
end if;
end process;
c1: DIVIDER port map(CLK, sq);
c2: DIVIDER10 port map(sq, sq10);
end Behavioral;
----------------------------------------------------------------------------
โปรแกรม Divider.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity DIVIDER10 is
generic (fin: integer := 50000000;
fout: integer := 20000);
port (CLK: in std_logic;
Q : out std_logic );
end DIVIDER10;
architecture RTL of DIVIDER10 is
signal COUNT : integer range 0 to (fin/(2*fout)) ;
signal qs : std_logic := '0';
begin
process (CLK)
begin
if CLK'event and CLK = '1' then
if (COUNT >= (fin/(2*fout)-1)) then
COUNT <= 0;
qs <= not(qs);
else
COUNT <= COUNT +1;
end if;
end if;
end process;
Q <= qs ;
end RTL;
โปรแกรม Divider10.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity DIVIDER10 is
generic (fin: integer := 20000;
fout: integer := 10);
port (CLK: in std_logic;
Q : out std_logic );
end DIVIDER10;
architecture RTL of DIVIDER10 is
signal COUNT : integer range 0 to (fin/(2*fout)) ;
signal qs : std_logic := '0';
begin
process (CLK)
begin
if CLK'event and CLK = '1' then
if (COUNT >= (fin/(2*fout)-1)) then
COUNT <= 0;
qs <= not(qs);
else
COUNT <= COUNT +1;
end if;
end if;
end process;
Q <= qs ;
end RTL;