Embedded Files
The Datapath
The Datapath
The control path (FSM)
The control path (FSM)
The Verilog Code
The Verilog Code
.ucf file
## 7 segment display
#7led
NET "a_to_g<0>" LOC = "H14";
NET "a_to_g<1>" LOC = "J17";
NET "a_to_g<2>" LOC = "G14";
NET "a_to_g<3>" LOC = "D16";
NET "a_to_g<4>" LOC = "D17";
NET "a_to_g<5>" LOC = "F18";
NET "a_to_g<6>" LOC = "L18";
NET "btn<0>" LOC ="B18";
NET "btn<1>" LOC ="D18";
NET "btn<2>" LOC ="E18";
NET "btn<3>" LOC ="H13";
#switch
NET "sw<0>" LOC = "G18";
NET "sw<1>" LOC = "H18";
NET "sw<2>" LOC = "K18";
NET "sw<3>" LOC = "K17";
#NET "sw<4>" LOC = "L14";
#NET "sw<5>" LOC = "L13";
#NET "sw<6>" LOC = "N17";
#NET "sw<7>" LOC = "R17";
# clock pin for Nexys 2 Board
NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
NET "reset_n" LOC = T3;
debounce module
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:35:08 01/05/2015
// Design Name:
// Module Name: debounce
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module debounce(d_in, reset_n,clk,d_out );
input [3:0] d_in;
input reset_n, clk;
output [3:0] d_out;
reg [3:0] delay1;
reg [3:0] delay2;
reg [3:0] delay3;
wire [3:0] d_out;
assign d_out = delay1 & delay2 & delay3;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
delay1 <= 4'b0000;
delay2 <= 4'b0000;
delay3 <= 4'b0000;
end
else
begin
delay1 <= d_in;
delay2 <= delay1;
delay3 <= delay2;
end
end
endmodule
addfsm module
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: CYCU EE Dept.
// Engineer: YK Lai
//
// Create Date: 15:33:56 12/31/2014
// Design Name:
// Module Name: addfsm
// Project Name:
// Target Devices:
// Tool versions:
// Description: A simple 4-bit + - calculator
//
// Dependencies: debounce.v, Nexys2_500General.ucf
//
// Revision: v1.0
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module addfsm(reset_n,clk,btn,a_to_g, sw);
input clk;
input reset_n;//hard reset directly from T3
input [3:0] btn;
input [3:0] sw;
output reg [7:0] a_to_g;
reg [24:0] q;
reg [3:0] result;
wire clk48;
wire clk24;
wire clk12;
wire reset; //from btn_de[0]
wire [3:0] sw_de;
wire [3:0] btn_de;
reg [3:0] sel_out;
reg [3:0] number_1 , number_2;
reg load;
reg add_sub;
reg select;
reg [2:0] state, next;
parameter [2:0] IDLE = 3'b000,
LOAD_ADD = 3'b001,
LOAD_SUB = 3'b010,
WAIT1 = 3'b011,
WAIT2 = 3'b100,
ADD_RESL = 3'b101,
SUB_RESL = 3'b110;
//Frequency Divider assume clk is 50Mhz
//assign clk48 = q[19];//48hz clock
//assign clk24 = q[20];//24hz clock
//assign clk12 = q[21];//12hz clock
assign clk6 = q[22];//6hz clock
//assign clk3 = q[23];//3hz clock
assign reset=btn_de[0];
//debounce module
debounce u1(sw, reset_n,clk6,sw_de);
debounce u2(btn, reset_n,clk6,btn_de);
//clock divider
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1'b0)
q <= 0;
else
q <= q + 1'b1;
end
//A loadable 4-bit register
always@(posedge clk6 or posedge reset)
begin
if(reset)
number_1 <= 4'd0;
else if (load)
number_1 <= sw_de[3:0];
end
// The calculator
always@(*)
begin
if (add_sub)
result <= number_1 + sw_de;
else
result <= number_1 - sw_de;
end
//Mux output
always@(*)
begin
if (select)
sel_out=result;
else
sel_out=sw_de;
end
//7-Segment LED Decoder
always @(*)
case(sel_out)
4'h0: a_to_g = 7'b0000001;
4'h1: a_to_g = 7'b1001111;
4'h2: a_to_g = 7'b0010010;
4'h3: a_to_g = 7'b0000110;
4'h4: a_to_g = 7'b1001100;
4'h5: a_to_g = 7'b0100100;
4'h6: a_to_g = 7'b0100000;
4'h7: a_to_g = 7'b0001111;
4'h8: a_to_g = 7'b0000000;
4'h9: a_to_g = 7'b0000100;
4'b1010 : a_to_g = 8'b10001000; //A
4'b1011 : a_to_g = 8'b11000000; //b
4'b1100 : a_to_g = 8'b11000001; //C
4'b1101 : a_to_g = 8'b10000010; //d
4'b1110 : a_to_g = 8'b01100000; //E
4'b1111 : a_to_g = 8'b01110000; //F
default: a_to_g = 7'b0000001;
endcase
///////////
//FSM Seq//
///////////
always @(posedge clk6 or posedge reset)
if (reset)
state <= IDLE;
else
state <= next;
////////////
//FSM comb//
////////////
always @(*)
begin
//next = IDLE;
load = 1'b0;
add_sub = 1'b1;
select=1'b0;
case (state)
IDLE :
begin
if (btn_de[1])
next = LOAD_ADD;
else if (btn_de[2])
next = LOAD_SUB;
else
next = IDLE;
end
LOAD_ADD :
begin
load = 1'b1;
next = WAIT1;
end
LOAD_SUB :
begin
load = 1'b1;
next = WAIT2;
end
WAIT1:
begin
if (btn_de[3])
next = ADD_RESL;
else
next = WAIT1;
end
WAIT2:
begin
if (btn_de[3])
next = SUB_RESL;
else
next = WAIT2;
end
ADD_RESL:
begin
select=1'b1;
add_sub=1'b1;
if (btn_de[0])
next = IDLE;
else
next = ADD_RESL;
end
SUB_RESL:
begin
select=1'b1;
add_sub=1'b0;
if (btn_de[0])
next = IDLE;
else
next = SUB_RESL;
end
default:
begin
next = IDLE;
end
endcase
end
endmodule
Page updated
Google Sites
Report abuse