This is a quick example to integrate a frequency divider, a 4-bit up counter and a 7-Segment decoder. The purpose is to show the counter values (0,1,2,...E,F) on top of the 7-segment LED
on your Nexys 2 board.
Please download the ucf file is at the bottom of this page.
Can you fix the bugs in the code?
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: CYCU EE
// Engineer:
//
// Create Date: 15:33:56 10/21/2014
// Design Name:
// Module Name: test for a 4-bit up-counter
// Project Name: test
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module test(reset_n,clk,a_to_g);
input clk;
input reset_n;
output reg [7:0] a_to_g;
reg [24:0] q;
reg [3:0] counter;
wire clk48;
wire clk24;
wire clk12;
//Frequency Divider assume clk is 50Mhz
assign clk48 = q[19];//48hz clock
assign clk24 = q[20];//24hz clock
assign clk12 = q[21];//12hz clock
assign clk6 = q[22];//6hz clock
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1'b0)
q <= 0;
else
q <= q + 1'b1;
end
//A 4-bit counter
always@(posedge clk6 or negedge reset_n)
begin
if(reset_n == 1'b0)
counter <= 4'b0;
else
counter <= counter + 1'b1;
end
//7-Segment LED Decoder
always @(*)
case(counter)
4'h0: a_to_g = 7'b0000001;
4'h1: a_to_g = 7'b1001111;
4'h2: a_to_g = 7'b0010010;
4'h3: a_to_g = 7'b0000110;
4'h4: a_to_g = 7'b1001100;
4'h5: a_to_g = 7'b0100100;
4'h6: a_to_g = 7'b0100000;
4'h7: a_to_g = 7'b0001111;
4'h8: a_to_g = 7'b0000000;
4'h9: a_to_g = 7'b0000100;
4'hA: a_to_g = 7'b0001000;
//4'hb: a_to_g = 7'b0;
//4'hC: a_to_g = 7'b0;
//4'hd: a_to_g = 7'b1;
//4'hE: a_to_g = 7'b0;
//4'hF: a_to_g = 7'b0;
default: a_to_g = 7'b0000001;
endcase
endmodule