The following labs will guide you through all the steps for schematic entry design of combinational logic by using Xilinx ISE 10.1 FPGA tools. You will learn how to perform:
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Lab1: Add files into a new design.
Lab2: 1-bit Buffer with LED (Schematic, Pin assignment, Configure FPGA Device)
Lab3: Multiplexer 2-1, 4-1, 7-Segment Led Decoder
Lab4: Flip-Flop, Register, Up Counter
Lab5: Counter (mod-6, mod-10, mod-60), Clock Divider
Lab6:De-Bounce, Scan