This is a bumb calculator. What's wrong with this code?
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:33:56 10/21/2014
// Design Name:
// Module Name: 4-bit Counter /w Pre-Load
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module test(reset_n,clk,btn,a_to_g, sw);
input clk;
input reset_n;
input [3:0] btn;
input [3:0] sw;
output reg [7:0] a_to_g;
reg [24:0] q;
reg [3:0] counter;
wire clk48;
wire clk24;
wire clk12;
wire load;
wire [3:0] outp;
reg [3:0] number_1 , number_2;
reg [3:0] delay1;
reg [3:0] delay2;
reg [3:0] delay3;
//Frequency Divider assume clk is 50Mhz
assign clk48 = q[19];//48hz clock
assign clk24 = q[20];//24hz clock
assign clk12 = q[21];//12hz clock
assign clk6 = q[22];//6hz clock
assign clk3 = q[23];//3hz clock
assign load= btn[1];
//debounce
assign outp = delay1 & delay2 & delay3;
always @(posedge clk3 or posedge btn[0] )
begin
if ( btn[0] == 1)
begin
delay1 <= 4'b0000;
delay2 <= 4'b0000;
delay3 <= 4'b0000;
end
else
begin
delay1 <= sw[3:0];
delay2 <= delay1;
delay3 <= delay2;
end
end
//clock divider
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1'b0)
q <= 0;
else
q <= q + 1'b1;
end
//A loadable 4-bit calculator
always@(posedge clk3 or posedge btn[0])
begin
if(btn[0] == 1'b1)
begin
number_1 <= 4'd0;
number_2 <= 4'd0;
end
else if (load)
number_2 <= outp[3:0];
else
number_1 <= outp[3:0];
end
always@(posedge clk3 or posedge btn[0])
begin
if (btn[0])
counter <=0;
else if (btn[2])
counter <= number_1 + number_2;
else if(btn[3])
counter <= number_1 - number_2;
end
//7-Segment LED Decoder
always @(*)
case(counter)
4'h0: a_to_g = 7'b0000001;
4'h1: a_to_g = 7'b1001111;
4'h2: a_to_g = 7'b0010010;
4'h3: a_to_g = 7'b0000110;
4'h4: a_to_g = 7'b1001100;
4'h5: a_to_g = 7'b0100100;
4'h6: a_to_g = 7'b0100000;
4'h7: a_to_g = 7'b0001111;
4'h8: a_to_g = 7'b0000000;
4'h9: a_to_g = 7'b0000100;
4'b1010 : a_to_g = 8'b10001000; //A
4'b1011 : a_to_g = 8'b11000000; //b
4'b1100 : a_to_g = 8'b11000001; //C
4'b1101 : a_to_g = 8'b10000010; //d
4'b1110 : a_to_g = 8'b01100000; //E
4'b1111 : a_to_g = 8'b01110000; //F
default: a_to_g = 7'b0000001;
endcase
endmodule