Advanced Packaging for 2.5D/3D Integration

2.5D/3D integration is an inevitable trend to overcome technical difficulties associated with saturation of Moore's law. Vertical interconnections such as through silicon via (TSV) and ultra-thin & high integration density interposer are key for 2.5D/3D integration. Our researches focus on the electrical design and characterization of interposers and vertical interconnections: design methodologies, optimization based on machine intelligence, co-design of chip-interposer-package-PCB, end-to-end analysis, and more. Recently, silicon interposer based on the CMOS process is widely used for HBM (2.5D) and wide-IO (3D). However, various companies are expecting other materials due to limited silicon wafer dimensions. Also, it is expected that overall interposer dimensions will continue to increase to accommodate more memories and surface mount devices for higher system bandwidth. Parallelly, we are focusing on silicon interposer and TSV related researches, and at the same time, looking for other candidates such as glass/organic packaging, fan-out wafer-level package (FoWLP). We defined the advantages and challenges of each candidate and looking for propersolutions.

In the packages, it is possible to embed various active and passive devices, plus even antennas. Not only 2D Re-distribution layers (RDL), but also vertical interconnections and embedded materials in the substrate can be used simultaneously to form 3D integrated passive & active components (3D IPAC). We are developing a novel noise suppression structure such as electromagnetic bandgap (EBG) structures and filters that can be embedded in the interposer. When we develop the new structure, we always focus on rout-ability and impacts on the signal/power integrity. Also, some structures might be suitable for a certain purpose, but they can become a source of EMI radiation. We always try to analyze possible issues and provide solutions to realize the signal/power integrity and EMC compliant design without sacrificing the rout-ability.