Recently, power supply voltages have been continuously reduced and as a result, noise margins are also reduced. As a result, it is difficult to separate noises generated by the channel properties and non-linear power/ground noises. Therefore, signal/power integrity must be considered and designed together. Our approaches are based on analytical modeling and statistics, which enable a fast and accurate SI/PI analysis. Recently, design complexity and the number of parallel buffers sharing the same power are increasing. Our SI/PI co-simulation methods provide promising solutions toward recent issues associated with complexity and simulation computational resources.

Electrical performance of the packages and interconnections can be a bottle-neck for the high-speed digital systems. Also, the design complexity of the packages and interconnections is continuously increasing. As a result, the possibility of design failures is increasing which can cause serious system malfunction, SI/PI, and EMC issues. Our researches/projects focus on chip-interposer-package-PCB co-design and co-analysis. We develop efficient simulation and modeling methods that can cover complex design, multi-power domains, and possible EM coupling between each hierarchy.

3D Integration is a key solution towards the saturation of Moore's law. To realize the 3D electrical system, a vertical interconnection is mandatory. There have been various researches related to SI and electrical modeling of the vertical interconnection such as TSV. However, vertical interconnections usually penetrate the power delivery network. Depending on locations, wave-properties, impedance, and even with material properties of the power delivery network, a large power/ground noise can be coupled to the vertical interconnections. In our researches/projects, we always consider this point and try to analyze and design the power delivery and high-speed vertical interconnections together.