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Work
2022.03 ~ Present Assistant Professor, EE, Jeonbuk National University
2025.01 ~ Present CEO, HB Inc. (High-performance semiconductor device)
2020.03 ~ 2022.02 Samsung Advanced Institute of Technology (SAIT), Staff Researcher
2018.03 ~ 2020.02 Purdue University (Prof. Peide D. Ye group), Postdoc, IN, US
2011.09 ~ 2013.12 Kookmin University, Industrial-University Researcher
2007.03 ~ 2009.06 Military Service (First Lieutenant, Signal Officer from R.O.T.C.)
Education
2014.03 ~ 2018.02 KAIST, Ph.D.
2009.09 ~ 2011.08 Kookmin University, M.S.
2003.03 ~ 2007.02 Kookmin University, B.S.
Activity
2020.03 ~ Present Committee, National Research Foundation
Next-Generation AI Semiconductor Project
-3D DRAM Architecture
-Smart Interconnection
-Logic/Memory & Brain-Inspired Devices
2016.03 ~ Present Member, IEEE Electron Device Society
2012 ~ Present Reviewer
-IEEE EDL, IEEE TED (Golden Reviewer: 2012~2018)
-APL, AIP Advances, APL Materials, JAP, Sci. Rep.
Contact
Email : hagyoul.bae@jbnu.ac.kr
Tel: 063-270-2404
#316 & 311, 7th Engineering building
Dep. of Electronics Engineering, Jeonbuk National University,
567 Baekje Road, Jeonju-si 54896
Awards/Media
2021 Excellence Paper Award from SAIT (Samsung Electronics) Aug 2021
▪ Low-Power and High-Density Ferroelectric Memory
2016 IEEE Electron Device Society Ph.D. Student Fellowship (the first winner in S. Korea) Dec 2016
▪ Awarded to 3 qualified students in each of the following geographical regions every year
: Americas, Europe/ Middle East/Africa, and Asia & Pacific
(https://eds.ieee.org/education/student-fellowships/phd-student-fellowship)
Excellence Award in 2017 SK Hynix Semiconductor Innovation Idea Contest Sep 2017
▪ Developed vertical DRAM with Si/SiGe superlattice bandgap engineered structure
(http://www.etnews.com/20171012000059)
▪ Linked to industrial-university cooperation research (2018-2020)
(Title: Simulation study for the optimization of DRAM performance)
▪ Transferred technology to SK Hynix (2018)
2017 KAIST 10 Outstanding Research Achievements (1st author) May 2018
▪ Developed 100% real fabric functional circuit beyond the von Neumann architecture for computing devices
(https://www.sedaily.com/NewsVIew/1RZN772ZDV)
(https://breakthroughs.kaist.ac.kr/wp/?x=0&y=0&s=memristor)
Bronze Prize in Samsung HumanTech Paper Award (1st author) Jan 2016
▪ Proposed a true fabric-type non-volatile memory using solution dip coating process
Top Researcher for Outstanding Research Achievements Jan 2016
▪ Awarded top 1 researcher in electrical engineering recipients of global Ph.D. fellowship funded by NRF of S. Korea
(https://issuu.com/kaistee/docs/2015_winter)
Water-Soluble Memory for Security Applications Jan 2016
(https://www.youtube.com/watch?v=fDZUbZNTW7U)
Grand Prize for Outstanding Research Achievements Apr 2015
▪ Awarded to top 1 student among the Ph.D. students in school of electrical engineering (KAIST)
Listed on 2018 Marquis Who’s Who in the World Sep 2017
Distinguished Poster Paper in the 2013 Society for Information Display (SID) (1st author) May 2013
▪ Proposed a novel characterization method for intrinsic donor- and acceptor-like density-of-states in
amorphous oxide semiconductor thin film transistors (AOS TFTs) by using photonic C-V data
(https://archi.kookmin.ac.kr/site/new/people.htm?mode=view&idx=1067112&sq=%B9%E8%C7%D0%BF%AD)
Best Paper Award in the 25th Korean Conference on Semiconductors (co-1st author) Feb 2018
▪ Analyzed radiation immunity and damage recovery in SiGe pMOSFETs
Excellence Award for Outstanding Research Achievements Apr 2017
▪ Awarded to top 3 students among the Ph.D. students in School of Electrical Engineering (KAIST)
Graduation Awards (Top Research Achievements) Aug 2011
▪ Awarded to top 3 students among all graduate students (Kookmin University)
Best Poster Paper Award in the 24th Korean Conference on Semiconductors (co-author) Feb 2017
▪ Analyzed parasitic resistance effect in 5-story vertically integrated junctionless NW FETs
Best Poster Paper Award in the 2015 IEEE Nano (co-author) Aug 2015
▪ Optimized low voltage operation of the Si-based mechanical switch
SK Hynix Paper Award in 17th Korean Conference on Semiconductors (co-author) Feb 2010
▪ Proposed gate capacitance modeling in leaky MOS systems using modified 3-element circuit model
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