The night vision headset is designed around the Tang Primer 25k FPGA to deliver maximum 549us of latency @60Hz night vision feed with thermal outline overlays. Additionally, the headset has an additional port to adapt any analog drone FPV receiver, creating a dynamic, low latency, utility headset for law enforcement, private security, inspection, and recreational use.
45.6ns to 549us of pixel-to-pixel latency
Custom 6 layer PCB
Complete digital night vision with HyperRAM and thermal integration
Firmware written entirely in Verilog
$550 BOM cost, $300 without thermal camera
312g, 24.7hr of battery life
Prototype versions testing the IR camera input and display output
Second prototype focusing on ESP32 functions in combination with FPGA timing for display and camera feed
Starting with the displays, I found these "0.2in FLCOS micro displays" from Aliexpress which use a driver board to convert CVBS into display data. For this project, I only needed the displays as they were, in theory, compatible with my FPGA. I reverse engineered their input, the I2C initialization data, and their power-on sequence, all without a datasheet, pinout table, or examples. The result is a VGA micro display which i can run entirely from 21 pins on my FPGA.