System On Chip

A system as described has the disadvantage of being large in size and consuming a lot of energy when operating while the demand for mobile devices, battery-powered devices, energy saving, compact size and reduced product costs is increasing. In addition, the demand for multi-functions and many utilities of customers is increasing. A traditional system using chips with low integration capabilities, few functions is difficult to meet customer needs and if it can meet them, the product cost may be high due to the use of more components, more complex and larger circuit boards, and larger products. For example, in the past, phones only had the function of listening, calling, texting; then added the function of saving and playing music; then taking pictures; then connecting to the internet, running applications, playing games; and now phones are no different from small computers. 

To meet the increasing demand for product utility, a chip increasingly integrates more functions and creates the concept of System on Chip. For example, the SoC chip below integrates an ARM CPU core and peripherals such as SegLCD, UDB, SCB, UART, CAN, SPI, ... 

Hardware Structure of SoC

As presented, each SoC chip has a different density of functional integration, but most SoCs have the following basic components:

CPU (Central Processing Unit) : The processor core is an indispensable component in an SoC that is responsible for managing all the main operations of an SoC. The CPU is responsible for the main processing flow in the SoC, coordinating operations between other components in the SoC, and executing the main calculations. A SoC can have one or more CPU cores. Some CPU cores:

• ARM CPU cores use ARM instructions and are products of ARM.

• RISC-V are CPU cores developed on the free and open RISC-V instruction set (riscv.org)

• SH (SuperH) uses the RISC instruction set developed by Hitachi and now a product of Renesas

System Bus : System bus is responsible for connecting different functional components in the microprocessor. System bus is like a path to transport data between components in SoC. Some system bus structures:

• AMBA (AXI, AHB, APB) is a bus standard developed by ARM

• CoreConnect is a bus standard developed by IBM.

• Avalon is a bus standard developed by Altera, now owned by Intel.

• STBus is a bus standard developed by  STMicroelectronic

• Wishbone  is a bus standard developed by  Silicore Corporation, now freely available on OpenCores

Memory : The memory inside a SoC is called internal memory to distinguish it from the memory that is outside the SoC and communicates with the SoC through the SoC's control pins. This internal memory can be:

• ROM: stores the initial configuration or program of the SoC

• RAM: used to store information or calculated values ​​during SoC operation

Internal control component (Internal block) : is a component that only controls operations inside the SoC without directly controlling any port of the SoC such as:

• Clock generator: Provides clock for all functional blocks in the SoC, including the CPU

• Reset generator: Provides reset for all functional blocks in the SoC, including the CPU

• Power management block: Controls power supply (on/off) for functional blocks in SoC

• Monitor blocks are blocks that have the function of monitoring the operation of the SoC, promptly detecting errors during operation to restart part or the entire system.

Peripheral: are blocks that can directly drive the pins (pins or ports) of the SoC to execute a control function outside the SoC, for example:

• UART: asynchronous serial data transmission and reception

• SegLCD: Controls display on LCD segment

• Video: Camera Control

• Audio: Audio recording and playback

• ADC: analog to digital converter

• ....

How to Design SoC ?

Let us assume that we have all the necessary functional blocks such as CPU, peripherals, system bus, etc. To build an SoC, we need to do the following basic tasks: 

1) SoC structure analysis: 

SoC structure analysis is to answer some of the following basic questions:

• What is the system bus structure of SoC?

• Which bus is this functional block (CPU, peripherals,...) connected to?

In this step, we need to determine which buses the system bus will include and how they are connected to each other. To determine the system bus structure, based on the scope of application, the masters and slaves will be selected. The basic information about the masters and slaves that will be in the SoC will be listed:

• Function and scope of application

• Data and address line width

• Operating frequency

First, based on the application scope that the SoC is aimed at (image display applications, data analysis, automatic control, ...) to group the Masters and slaves according to different priority levels. For example, we need to build a SoC dedicated to real-time sensor data sampling and analysis, then the number 1 priority group must be the peripherals related to this function such as ADC (used to convert analog signals from sensors to digital signals). Thus, it needs to be arranged so that the data exchange from ADC to masters is the fastest.

The next basis is based on the processing speed or operating frequency of the master and slave. High-speed components need to be attached to high-speed buses, low-speed components will be attached to the corresponding low-speed buses.

Based on the data bus width, attach the master and slave to the bus with the appropriate data bus width.

After completing this step, we will have the SoC structure as shown in Figure 6 and a description of the bus communication showing bus frequency; number of masters, slaves; data line width,...

In the example in figure above the system consists of 1 AHB bus and 2 APB buses both with a maximum frequency of 32 Mhz. 

2) Detailed analysis

In this step, we need to clearly analyze the following issues:

• Which slaves can a master access and over which buses?

• Which masters and through which buses can a slave be accessed?

• What is the address range of each slave? from which address to which address?

3) System connection

Connect the masters and slaves to the buses as analyzed.

4) Check connection

Perform syntax error checking using specialized software such as Leda, Spyglass to ensure the connections are correct. If this connection is done through a specialized software for building SoC, the connections are usually checked and warned during the SoC building process.

5) Functional testing

Perform system level simulation to ensure that all masters can access their slaves within the specified address range. If access is outside the specified address range, the system will still operate smoothly but there will be a warning mechanism.

Note, this step is not to simulate the functions of the system components such as testing the functions of the video block, UART block or any other block, but only to test the continuity of the built SoC system.

6) Performance testing

Perform test simulations to ensure that the access bandwidth of masters to slaves or memory meets the requirements. The access of masters, especially priority masters, must be completed within an allowable time period. If not achieved, the SoC will not meet the desired performance. For example, the DSP master must always be guaranteed a memory read bandwidth of 10 Mbps (this is just an illustrative example, not meant for practical application) to calculate and give timely results. Even if all masters in the SoC are accessing the memory, the SoC system must still ensure 10 Mbps for the DSP master.

References

1. https://nguyenquanicd.blogspot.com/2018/05/background-soc-system-on-chip.html

2. https://www.maven-silicon.com/blog/what-is-system-on-chip-soc-in-vlsi/

3. https://vlsifacts.com/what-is-an-soc-in-vlsi/