• Goal: Expand the RTL design into an intermediate logic netlist and bind the subblocks to the loaded library. The tool converts the RTL description into Boolean expressions and technology-independent logic structures.

• To do: Use a command like elaborate <Top> to compile the design into an internal form. "elaborate toplevel" This command pre-compiles, parses all submodules, parameters, and always/always_flip-flop blocks into basic logic. The tool also infers states, encodes signals, and identifies register inferences.

• Output: The design is fully “extended” with all connections between signals and logic components. Submodules have been provisionally mapped to generic elements, and flip-flops, muxes, and memories have been identified. The result is a technology-independent netlist, including all logic cells (represented generically) and ready for the next optimization step.

• Example: After reading the file, run the command: "elaborate toplevel" , the tool will display a report about the design structure. For example, it reports the number of flip-flops, muxes created. The result inside is a logical (unmapped) netlist that fully represents the design's functionality.

• Objective: Set design constraints such as clock frequency, input/output latency, clock tolerance, etc. so that the tool knows the timing requirements and performance targets. This step guides the synthesis process towards specific targets (speed, area, etc.).

• To do: Define the corresponding SDC (Synopsys Design Constraints) commands. For example:

create_clock -period 10 [get_ports clk]; # clock 100 MHz

set_input_delay 6 [get_ports din];

set_output_delay 6 [get_ports dout];

Then the SDC file can be read :

dc_shell> read_sdc -verbose constraints.sdc

Commands such as set_clock_latency, set_max_area can also be used. As mentioned, “check carefully that all constraints are accepted by the tool”.

• Output: All timing and other constraints have been loaded into the tool. The tool stores information about the clock period, input/output delays, and size constraints. This information will be used to compare the results after each optimization step.

• Illustrative example: Example in Synopsys DC :

dc_shell> create_clock -period 5 [get_ports clk] 

dc_shell> set_input_delay -clock clk 2 [get_ports din]

dc_shell> read_sdc constraints.sdc

• Goal: Optimize logic while it is still generic (not yet fixed technology) to reduce the number of gates, minimize delay, power… Some transformations include collapsing Boolean expressions, eliminating dead logic, refactoring circuits, etc.

• To do: The tool performs logic optimization algorithms: for example, constant folding (pre-calculating constant operations), constant propagation (propagating constant values), dead code elimination (eliminating circuits that do not affect the output), factorization, retiming (adjusting flip-flop positions), sharing common sub-expressions… . These transformations take place when the design is not yet mapped, so the tool can flexibly change the logic representation to make the circuit neater.

• Output: Optimized generic netlist: the number of logic gates and logic depth are often reduced, eliminating gates that almost only work with constants. The design is still technology-independent but “more compact” and has better quality than the original.

• Example: Simple example of constant folding :

assign out = a & 1'b1; // → assign out = a;

• Objective: Map the optimized logic netlist to the specific technology library, i.e. select cells (gates, FFs, etc.) from the library to implement Boolean functions in the design.

• To do: Run the synthesis tool in map mode (Synopsys DC: synthesize -to_mapped, Cadence: compile) to convert each piece of generic logic into specific cells. The tool uses a tree-covering algorithm to optimize the cost (delay, area) of the logic nodes compared to the library. Example with DC :

dc_shell> synthesize -to_mapped -effort medium

according to the tutorial slide, this command will perform the mapping with a moderate level of optimization.

• Output: A complete gate-level netlist, where each element is now a cell from the loaded library. The design is now represented by specific physical elements, with information about the size and delay of each cell.

• Example :

read_sdc sdc/constraints.sdc

synthesize –to_mapped –effort medium

• After this command, DC will output the mapped netlist to the technology library (including internal adjustments to satisfy constraints if any).

• Objective: Fine-tune the technology netlist after mapping to best meet the design requirements (time, area). At this stage, the tool can change cell size, insert buffers, retime (move FFs), or adjust booleans at the technology level to improve the results.

• What to do: Call additional optimization commands on the mapped netlist, for example in DC use compile or compile_ultra for comprehensive optimization. The tool will try advanced transformations (e.g. increase drive, change logic expression, insert BUFs, etc.) to reduce the delay on the critical delay line or reduce the area according to the target. Usually after each optimization, we check the design again with check_design.

• Output: The final netlist is optimized according to the set constraints. This is the netlist prepared for the export step. It best meets timing goals (hitting target latency) and other requirements (e.g. saving space or power).

• Example : in DC run command

dc_shell> compile_ultra

• Objective: Synthesize the result information and write a report (time, area, power, etc.), and export the final netlist file. This is the final output of the synthesis process, serving the place & route step or the next verification steps.

• To do: Use the tool's report commands to view the results. For example, in DC, you can use report_timing, report_area, report_power, report_qor to write the corresponding reports. Then export the technology netlist to an external file (Verilog/VHDL/EDIF) using commands such as write -format verilog -output netlist.v.

• Example : 

report_timing -num_paths 10 > reports/timing_reports.rpt

write_hdl > export/netlist.v

The equivalent write -format verilog command will write the structural netlist in Verilog format. In addition, it is possible to export standard SDF files (write_sdf), SDC files (write_sdc), power reports (write_pow), etc.