Embedded Files
1.Goals of Logic Synthesis ?
1.Goals of Logic Synthesis ?
Minimize area
In terms of literal count , cell count , register count , etc.
Minimize power
In terms of switching activity in individual gates , deactivated circuit blocks , etc.
Maximize performance
in terms of maximal clock frequency of synchronous systems , throughput for asynchronous systems
Any combination of the above
Combined with different weights
Formulated as a constraint problem
More global objectives
Feedback from layout
Actual physical sizes , delays , placement and routing.
2. Inputs of Logic Synthesis ?
2. Inputs of Logic Synthesis ?
RTL(.v) : Verilog file describes digital circuit at Register Transfer Level.
Constraints (.sdc) : Timing constraint file, written according to Synopsys Design Constraints standard.
Technology library (.db) : Chip manufacturing technology standard library file, defining standard cell characteristics.
3. Outputs of Logic Synthesis ?
3. Outputs of Logic Synthesis ?
Gate-level Netlist(.v) : Circuit description after synthesis, mapped to cell in technology library.
Scripts Verification File(.svf) : Used for formal verification between the original RTL and the gate-level netlist to ensure no functional changes after synthesis.
Synthesis Design Constraints(.sdc) : Timing constraints.
REPORTS : Timing , Area , Power , QoR reports.
Standard Delay Format(.sdf) : Contains delay information of cells & nets after synthesis.
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