Though gate-level modeling is easy to implement for the designs when the number of gates becomes more in the design, it becomes difficult for the implementation. Hence, higher-level abstraction is required for design implementation.
The data flow modeling provides a way to design circuits depending on how data flow between the registers and how data is processed.
In data flow modeling, a continuous assignment is used to drive a value to a net or wire. A continuous assignment statement is represented by an ‘assign’ statement.
Syntax:
assign <expression or net> = <constant value or expression>
Example:
//Regular continuous assignment
wire result;
assign result = i1 ^ i2;
//Implicit continuous assignment
wire result = i1 ^ i2;
The L.H.S. of an assignment must be always a vector or scalar net or a concatenation of vector or scalar nets. It can not be a vector or scalar register.
The R.H.S. of an assignment can be registers or nets or function calls. Here, registers or nets can be vectors or scalars.
Since continuous assignments are always active, as soon as the R.H.S. operand has any changes, it assigns to the L.H.S. operand.
assign LHS = RHS
Excercise: Write Verilog program to describe AND, OR, XOR gate.