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What is Net Types ?
What is Net Types ?
In SystemVerilog, net types are used to model physical connections between components in digital circuits. They do not store values, its value is determined by the values of its drivers and the default value of a net is typically 'z' (high impedance) when left unconnected.
Net assignment:
Nets are used for driving signal
Only using the keyword assign to assign a signal to a net.
Must be assigned outside procedure blocks like initial, always,…
Usually use wire and tri in Verilog and SystemVerilog programs
Wire and Tri net
Wire and Tri net
Wire and tri are two types of nets in Verilog that serve as connections between elements in a digital circuit model. While they are functionally identical and share the same syntax, they are given different names to help designers convey the intended purpose of the net within the model.
Wire nets:
Typically used for connections driven by a single source
Ideal for representing nets controlled by one gate or one continuous assignment
The name "wire" suggests a simple, unidirectional connection
Tri (short for tristate) nets:
Commonly used for nets that may have multiple drivers
Suitable for modeling buses or other shared connections where different components might drive the net at different times
The name tri implies the possibility of multiple drivers and the potential use of high-impedance states
When multiple drivers of the same strength drive conflicting values on a wire or tri net in Verilog, the result is indeed an unknown (x) value.
Wired net
Wired net
Wired nets are of type wor, wand, trior and triand and are used to model wired logic configurations.
The wor and trior nets are designed to implement wired OR configurations, ensuring that the net's value becomes 1 whenever any of the drivers outputs a 1.
The wand and triand nets are designed to implement wired AND configurations, ensuring that the net's value becomes 0 whenever any of the drivers outputs a 0.
Example:
// Code your testbench here
// or browse Examples
module net_ex;
wire single_wire; // a single wire
tri two_port; // a two-port driver (tri allows multiple drivers)
wire [7:0] bus; // an 8-bit bus
// Assign constant values
assign single_wire = 1'b1;
assign bus = 8'b1001_0111;
// Multiple drivers on tri type net
assign two_port = 1'b1;
assign two_port = 1'b1; // Conflicting driver
initial begin
#1; // Wait for assignments to take effect
$display("single_wire = %b", single_wire);
$display("bus = %b", bus);
$display("two_port = %b", two_port);
end
endmodule
References
References
Book System Verilog for Verification by CHRIS SPEAR
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