Timing Concepts

The majority of digital designs are Synchronous and constructed with Sequential Elements. 

• Synchronous design eliminates races (like a traffic light). 

• Pipelining increases throughput. 

Timing Arc

Sequential arcs are between the clock pin and either input or output pin. Setup and hold timing arcs are between the input data pin and clock pin of flip flop and are termed as timing check arcs as they constrain a form of the timing relationship between a set of signals. Sequential delay arc is between clock pin and output Q pin of FF. An example of a sequential delay arc is clk to q is called delay arc and clk to D input is called timing check arcs in sequential circuits

Timing Parameters

Tcq 

Propagation Delay

Slew of a Waveform

Tsetup - setup time

Thold - hold time

Skew can be defined as positive if the receiving register receives the clock later than the transmitting register or negative in the opposite case. Clock skew becomes a serious problem in digital design as it can violate the timing constraints that the synchronous circuits rely on. 

For example, given a constant clock frequency and negative skew, as shown in Figure below, the clock arrives at the receiving register B much earlier than the transmitting register A. In this case, the data sent out from the transmitting register will arrive at the receiving register after the clock arrives. Here, the data does not meet the setup and hold requirements of the receiving register (i.e., the data was not readily available at the receiving register at the time of clock arrival). Due to this, data will be lost since the receiving register cannot latch the data securely. This concept would then have a compounding effect, as future logical operations that rely on the lost data would also fail.

Quick intuition:

• Positive skew: the clock arrives later at the receiving register than at the transmitting register.

• Negative skew: the clock arrives earlier at the receiving register than at the transmitting register.

Impact on timing constraints (with this definition):

Setup (max path):

Tclk-q(max) + Tcomb(max) + Tsetup -skew ≤ Tclk

→ Positive skew helps setup (reduces the left-hand side), negative skew makes setup harder.

Hold (min path):

Tclk-q(min)+Tcomb(min)  ≥  Thold + skew

→ Positive skew makes hold harder (increases the right-hand side), negative skew helps hold.

Quick example:

• Tclk-q(max) = 120ps, Tcomb(max)=380ps, Tsetup=50ps.

  • Negative skew: 120+380+50=550 ps ⇒ need Tclk≥550ps ⇒ need Tclk ≥ 550ps (≈1.82 GHz). 

  • Positive skew +80+80+80 ps: need Tclk ≥ 470 ps (≈2.13 GHz) ⇒ easier to meet setup.

• For hold: tclk-q(min)= 60 ps, Tcomb(min)= 40 ps, thold= 30 ps.

  • No skew: 100 ≥ 30(OK).

  • Positive skew +80+80+80 ps: require 100 ≥ 110 ⇒ hold violation.

👉 Rule of thumb: Positive skew helps setup but hurts hold (under your definition).

Timing Constraints

There are two main problems that can arise in synchronous logic: 

• Max Delay : The data doesn’t have enough time to pass from one register to the next before the next clock edge. 

• Min Delay : The data path is so short that it passes through several registers during the same clock cycle. 

Max delay violations are a result of a slow data path, including the registers’ tsetup, therefore it is often called the “Setup” path. 

Min delay violations are a result of a short data path, causing the data to change before the thold has passed, therefore it is often called the “Hold” path. 

Setup (Max) Constraint

Let’s see what makes up our clock cycle: 

• After the clock rises, it takes Tcq for the data to propagate to point A. 

• Then the data goes through the delay of the logic to get to point B. 

• The data has to arrive at point B, Tsetup before the next clock. 

In general, our timing path is a race: 

• Between the Data Arrival, starting with the launching clock edge.

• And the Data Capture, one clock period later. 

Hold (Min) Constraint

Hold problems occur due to the logic changing before thold has passed. 

This is not a function of cycle time – it is relative to a single clock edge! 

Let’s see how this can happen: 

• The clock rises and the data at A changes after Tcq. 

• The data at B changes Tpd(logic) later. 

• Since the data at B had to stay stable for Thold after the clock (for the second register), the change at B has to be at least thold after the clock edge. 

Timing Paths

There are four categories of timing paths: