The Library Definition stage of the logic synthesis process tells the synthesis tool where to find the standard cells and IP libraries for binding and mapping. The tool is provided with a path to the library directory, the specific name of the specified standard library (usually a specific mode angle), and .lib files for IP blocks such as memory, I/O ports, etc. The standard library is a collection of logic gates that have been defined and detailed in terms of area, timing, and power (as shown in the slide), giving the synthesis tool important information when generating gates and optimizing the logic network.
Each standard library includes a variety of cell types, meeting the needs of digital design :
Combinational logic cells: Basic logic gates (NAND, NOR, INV, …) with different levels of drive strength.
Complex cells (AOI, OAI, etc.): Complex cells (help reduce the number of logic levels).
ECO Cells: Special cells used for post-processing (Engineering Change Order).
Buffers/Inverters: Signal buffers and invertors with different drive strengths.
Clock cells: Clock cells with balanced up/down delay (avoid skew).
Delay cells, Level Shifters: Delay cells, voltage shift cells (HL, LH).
Sequential Cells: Flip-flops and latches with variety (positive/negative edge, reset/set sync/async, Q/QB, enable, scan,…).
Physical Cells: Physical cells such as fillers, tap cells, antenna cells, endcaps, tie cells… (used to ensure density, connect power circuits, prevent noise).
This content shows that the standard cell library is very diverse, including all the basic and auxiliary components needed in digital design. Having these cells available allows the synthesizer to easily use them when needed (e.g. create latches, create buffers, add voltage switching cells).
Buffer/inverter cell: serves to amplify the signal, often has many large/sub levels to balance between area and load driving ability.
Each type of logic cell usually has many levels of drive strength (symbols X2, X3, D2, D3, ...): large drive level (large output stage) can push the load farther better but takes up more space and has larger leakage, while small drive saves space/power.
In addition, the library supports Multi-Threshold CMOS (MT-CMOS): meaning that the same cell can have a version that changes the gate capacitance (bias via mask) to change the threshold voltage (High-Vt, Low-Vt, Standard-Vt). All these threshold versions have the same footprint (geometry), so they can be interchanged without rearranging.
Clock Cells: special cells that balance the rise/fall delays to reduce skew on the clock line; usually specially designed pads or latches.
Normal cells are optimized for speed, but do not guarantee balanced up/down delays. This is not good for the clock circuit, because if the up and down delays are not balanced, it will cause unwanted skew. Therefore, libraries provide dedicated clock cells with balanced up/down characteristics to reduce skew. However, these cells are not optimized for normal data and are rarely used.
Normally, only use standard buffer/inverter on clock line, unless need to combine CKG (gated clock) then use integrated clock gate
Sequential cells: flip-flops and latches with rising/falling edge options, synchronous/asynchronous reset, Q/QB, with or without scan support.
These are important building blocks for realizing synthesized registers and FSMs. For example, when synthesizing from Verilog with always @(posedge clk) , the synthesizer will use these flip-flop cells. The variety (e.g. synchronous or asynchronous set/reset) allows for flexible design according to feature requirements (e.g. scan test or fast reset).
Level shifter: used to transfer signals between different voltage regions on the chip.
HL (High-to-Low) shifter :
Requires only one voltage
Signle height cell
LH (Low-to-High) shifter :
Needs 2 voltages
Often double height
Filler cells are used to fill the gaps in the standard cell row, ensuring continuity of the diffusion and well layers according to the design rules. They must be inserted into the gaps in the cell row to satisfy the density rules of the base material layers.
For example, filler cells provide inactive MOS regions or dummy poly components for modern IC technologies, avoiding overly empty regions that are difficult to fabricate. Even at the two edges of a cell row, End Caps – special filler cells – are often needed to terminate the row and maintain continuity of the well/diffusion structure.
In addition, the library can also add MOS capacitor (MOSCAP) filler cells between VDD and GND (called DeCAP cells) to stabilize local voltage, acting as noise filtering capacitors right in the physical layer of the chip.
=> In short, filler cells are crucial for ensuring manufacturability and reliability of the layout: without them, density rules can be violated or large, uncontrollable voids can be created, leading to errors in the chip fabrication process.
Within this same physical cell category are also Tap cells (anchor cells or hook cells). The primary purpose of a tap cell is to provide a low-resistance connection between the wells or substrate and the voltage supply line (VDD/VSS). Specifically, a tap cell is a non-logic cell that has a “well tie” and/or “substrate tie” built in.
Tap cells are typically inserted into the cell row at regular intervals as specified by the design rules. This ensures that the local well voltage is always fixed to the source, preventing latch-up due to the formation of a shorted semiconductor path between VDD and GND. (Latch-up occurs when unwanted parasitic transistors turn on, creating a current from VDD to GND, resulting in complete damage to the IC.)
Tap cells act as “runaway current guides” for the wells to keep the voltage inside the transistors correct, avoiding parasitic transistor activation. Typically, tap cells do not need to be placed behind each individual cell; instead, they are spaced appropriately to ensure voltage safety while also allowing for “bias” to be applied to each well or base to optimize performance and leakage.
For example, in triple-well technologies, the N-well can be anchored to a voltage other than VDD, or the P-well base can be anchored to a voltage other than VSS, to control the transistor threshold. In short, tap cells are important because they ensure that the wells are well anchored, prevent latch-up, and stabilize the transistor threshold during operation.
Engineering Change Order (ECO) Cells : is a late engineering change in the chip design process, typically made after the place-and-route step or even after the silicon has been taped out.
The purpose of ECO is to fix minor bugs or add necessary features that arise near the end of the project, without having to remanufacture the entire chip mask.
For example, when a change is discovered after the chip has been laid out, manufacturers often update the design by adding a few layers of metal (a technique called “metal-fixing”) rather than redesigning the entire design. To help with this, a number of ECO cells (also called spare cells or bonus cells) are often included in the chip layout. These cells initially have no function in the circuit (they do not appear in the logic netlist) but are pre-inserted into empty slots in the layout.
When ECO is needed, engineers simply redesign the metal mask and via to connect the transistor pins of the ECO cells to each other or to the desired signal lines. Thanks to that, ECO cells can be quickly “loaded” with functions into basic logic gates such as AND, NAND, XOR, FF, MUX, ... or combine them to create more complex functions.
For example, two NAND gate ECO cells can be connected to form an AND gate when needed. ASIC standard libraries typically define these ECO cells (with special names or symbols) so that the EDA tool can recognize them and keep them idle until they need to be “activated” with a new mask. With ECO cells, designers can fix or optimize logic signals with low cost (just adding a few layers of masks) without having to go back to the complex synthesis and placement/layout stages.
👏In summary, both cell types play a particularly important role in ASIC design: filler and tap cells ensure the availability of the layout by maintaining continuous layers of material and preventing physical problems (such as latch-up), while ECO cells allow the flexibility to make late modifications to the circuit by storing alternative logic (and then connecting it with a mask). This allows ASIC designs to achieve both high performance and reliability in manufacturing and operation.
Behavioral views: Verilog/Vital descriptions for simulation and logic equivalence verification.
Physical views: GDSII layouts for DRC, LVS, custom layouts.
Abstract views: LEF files for P&R and RC extraction.
Transistor-level: Spice/Cdl netlists for LVS and transistor simulation (usually with/without parasitics).
Timing/Power: Liberty (.lib) files containing timing, power properties for Static Timing Analysis.
Power Grid: needed for IR voltage drop analysis.
Other: symbols (for display), OpenAccess library (joined by Virtuoso).
At the end of the slide there is a table illustrating the file names: .v (behavior), .lef (abstract), .gds (layout), .spi/.cdl (spice), .lib (timing), .oa (OpenAccess). Summary: a standard cell library is essentially a collection of files, each serving a different tool/task in the design (synthesis, routing, timing analysis…).
📝Library Exchange Format (LEF) is an ASCII format that describes the abstract layout interface used in the Place & Route step. Highlights of LEF include: it describes the simple geometry of each cell (width, height, symmetry point) and pin location of the cell, but does not contain transistor details or poly/diffusion information. LEF format helps the locator and router know what obstacles and predefined grids the cell must follow.
🟪Technology LEF includes design rules and technology information such as metal layer names, via parameters, wire spacing and width, and site information used to order cell tracks. Cell LEF lists each cell in the library: cell name, classification (core/pad), dimensions (width × height), symmetry (x, y), and pin details (pin name, signal direction, metal layer, e.g. ANTENNAAREA) for proper connection by P&R tools. LEF thus provides an abstract description of the cell, reducing layout data to a lightweight form that P&R can use effectively. Layout interface points such as cell outlines and pin locations are specified in the LEF file.
Layers: Name (M1, M2,…), type (routing or cut/via), electrical properties (resistance R, capacitance C).
Design Rules: Spacing, Width, Direction,…
Antenna data: Antenna effect calculation information.
SITE: Defines the library grid size. For example, CORE is the standard site using the smallest cell size (like 0.2x12.0 in the code example).
CORE site: Site parameters for the basic approximate cell, example code for the CORE site with size 0.2 x 12.0.
Via definitions: Defines the vias (VIA class).
Units, Grids: Units of length and grid layout.
Example LEF file: SITE CORE definition, MET1 class definition (type ROUTING, PITCH, WIDTH, SPACING, horizontal direction, R per sq, C per sqdist) and VIA (type CUT).
Note: there may be an additional file for parasitic citation rules (cap tables, techfile QRC) included with PDK.
Meaning: P&R tool uses this information to know the library grid, micro width, best wire direction,... to help place and connect accurately, and also allows initial estimation of line resistance, capacitance.
Cell height: Measured by the number of “tracks” (pitch of M1).
For example, an 8-Track cell allows 8 horizontal M1 wires. More tracks means wider transistors, higher speed, but also larger area. 7-8 track height library is good for cross-section, 11-12 track is good for performance but high leakage, 9-10 track is average.
Parameter example: Cell height = H (number of tracks), Power rail width W1, Vertical grid W2, Horizontal grid W3, N-Well height W4 (bottom table) shows the values.
Cells must fit the grid definition (SITE). The minimum cell is SITE (cell height X cell width), which must be a multiple of the subcell and row height. Cells can be double the height. Pins should coincide with the wire track to facilitate higher metal connections.
The illustration shows the vertical/horizontal grid alignment and the origin of the cell, PR boundary (Power Rail boundary). The SITE CORE example code asserts the site definition (CLASS CORE, SYMMETRY X Y, SIZE 0.2x12.0).
Role: this information is important for P&R, ensuring that all cells are properly placed on the grid, pins are in the correct position for automatic wiring, and that power, grid, and PR boundary parameters are clearly defined in the LEF.
The Liberty (.lib) format is a file that describes the timing, power, and other characteristics of standard cells in a given technology. This data is extracted by SPICE simulation and stored as a lookup table so that STA and logic synthesis tools can quickly calculate the delays of circuits.
Instead of running SPICE (which is too complex and slow for millions of cells), STA uses the timing models in the .lib to estimate the propagation delay (tpd) and the trie, tfall of each signal path.
According to the picture, the goal is to “for each timing arc, calculate the Propagation Delay and Output transition based on the Input transition and Output Load”.
Each .lib file typically contains information on one corner – that is, a specific combination of process, voltage, temperature, etc. (PVT) corners – for timing analysis or synthesis under that condition.
The .lib file has a hierarchical structure consisting of library, cell, pin, and timing groups. The first part (Library level) declares general information of the entire library such as operating conditions, units, wireload model, distribution lookup table, etc.
For example, wire-load model parameters are often defined here. Each standard cell (cell) is described in a cell (cell_name) {...} block which includes general properties (function, area, …) and pin groups (pins). Each pin in the cell is declared in pin (pin_name) { … }, which defines the function, statics, as well as timing blocks to contain the arc-specific delay model.
For example, each input-output arc is defined by timing arcs with attributes such as propagation delay (TPD), transition time (trise, tfall), input slew, etc.
Thanks to this structure, the STA tool can quickly retrieve the delay and power of each component when analyzing the circuit; at the same time, the logic synthesizer also knows the basis for generating the appropriate netlist.
The NLDM model is one of the most traditional timing models in the .lib file. As shown in the image, NLDM uses a “ramp voltage source + fixed resistor” model for the driver and a min/max cap value for the receiver. The delay and switching time are calculated through a non-linear lookup table with two input variables: the input signal slope and the output load capacitance. The advantage of NLDM is that it is extremely fast and simple (because it only uses look-up tables).
However, NLDM cannot simulate the change in capacitance during switching (capacitive coupling) and is inaccurate at technology smaller than ~130nm. In other words, NLDM works well at older nodes (above 130nm) but as technology advances to nanometers, the error can be very large.
Therefore, today's industry standards often recommend using NLDM only in early design steps (e.g. mockups) or situations that do not require a high level of accuracy.
To overcome the shortcomings of NLDM, nonlinear current source-based models are proposed, including CCS and ECSM.
As shown in the figure, the CCS/ECSM model treats the output of the digital cell as a nonlinear current source circuit instead of an ideal voltage source. This allows the model to more accurately reflect the actual current changes when the switching input signal and load capacitance change. In CCS/ECSM, the controller is described as a nonlinear current source, and the receiver has a dynamically changing capacitance.
The downside is that more data is needed (multiple lookup tables, even voltage wave data) and the calculations are a bit more complicated. In return, the accuracy increases greatly: as shown in the figure, CCS/ECSM achieves an error within 2% of the SPICE result and is a mandatory method for advanced nodes below 130nm.
In summary, CCS/ECSM is used in the final design step (sign-off) for the most reliable delay and power consumption, while NLDM is mainly used in the earlier stages for speedup.
The wireload model is a feature in the library file to estimate the resistance and capacitance of signal wires when the actual layout (pre-layout) is not known. Specifically, the image shows that the Wireload Model will determine the wire length based on the number of fanouts (the number of pins that the net connects). For example, the library can define a fanout_length table for each fanout value to estimate the wire length and from there calculate the linear R and C per unit length.
The idea of the wireload is to allow the synthesis and initial STA to predict the delay due to the wire before the plane design is done. However, the major drawback of the Wireload Model is that it is not accurate at nanometer technology. According to the image, because this model is too coarse and static, it leads to large discrepancies between the synthesis stage and after the layout on small technology nodes. For example, generic fanout-based wire resistance/capacitance estimates often do not reflect the actual geometry of modern chip layouts and microelements. Therefore, in modern processes, engineers often use “physical-aware synthesis” or layout-aware iterative design (Synopsys calls Topographical mode, Cadence calls Physical Synthesis) to more accurately calculate wire loads instead of using traditional Wireload.
🟪In summary, the Liberty standard library definition file (.lib) is an important source of information for STA and logic synthesis: it provides timing/power information for each cell based on a specific PVT condition. The file is organized in a hierarchical structure (library → cell → pin → timing) that allows electronics tools to quickly retrieve the necessary data. The NLDM, CCS, ECSM delay models in the .lib represent different calculation methods – from simple lookup tables (NLDM) to complex current source models (CCS/ECSM) – with trade-offs between calculation speed and accuracy. Finally, the Wireload Model supports rough but less accurate wire delay estimates on small technology. This knowledge is essential for students and VLSI engineers to understand how CAD tools use library information during circuit design and analysis.
LEF (library exchange format): Contains the technology information and physical abstraction library of the Standard cell provided by the factory
Cell information (size, pin position, blocking area).
Definition of the connecting metal layer (via)
Design rule (Minimum distance, length, width, .....)
Does not contain information about the actual location or connection
DEF (design exchange format): Contains the actual layout information of the layout
Location of specific cells / macros on the layout
Netlist (shows how cells are connected on the layout)
Connecting specific signal routing areas together (Routing)
Actual size of silicon area on wafer (DieArea)
🟪 In summary :
LEF: Used to contain information about the design rules that the factory can produce.
DEF: Contains specific connection design information, size, actual layout of cells, pads, macros on the layout and is constrained by the design rule from LEF