• Combinational logic cells: Basic logic gates (NAND, NOR, INV, …) with different levels of drive strength.

  • Complex cells (AOI, OAI, etc.): Complex cells (help reduce the number of logic levels).

  • ECO Cells: Special cells used for post-processing (Engineering Change Order).

• Buffers/Inverters: Signal buffers and invertors with different drive strengths.

  • Clock cells: Clock cells with balanced up/down delay (avoid skew).

  • Delay cells, Level Shifters: Delay cells, voltage shift cells (HL, LH).

• Sequential Cells: Flip-flops and latches with variety (positive/negative edge, reset/set sync/async, Q/QB, enable, scan,…).

• Physical Cells: Physical cells such as fillers, tap cells, antenna cells, endcaps, tie cells… (used to ensure density, connect power circuits, prevent noise).

   This content shows that the standard cell library is very diverse, including all the basic and auxiliary components needed in digital design. Having these cells available allows the synthesizer to easily use them when needed (e.g. create latches, create buffers, add voltage switching cells).

• Filler cells are used to fill the gaps in the standard cell row, ensuring continuity of the diffusion and well layers according to the design rules. They must be inserted into the gaps in the cell row to satisfy the density rules of the base material layers.

• For example, filler cells provide inactive MOS regions or dummy poly components for modern IC technologies, avoiding overly empty regions that are difficult to fabricate. Even at the two edges of a cell row, End Caps – special filler cells – are often needed to terminate the row and maintain continuity of the well/diffusion structure.

• In addition, the library can also add MOS capacitor (MOSCAP) filler cells between VDD and GND (called DeCAP cells) to stabilize local voltage, acting as noise filtering capacitors right in the physical layer of the chip.

=> In short, filler cells are crucial for ensuring manufacturability and reliability of the layout: without them, density rules can be violated or large, uncontrollable voids can be created, leading to errors in the chip fabrication process.

• Within this same physical cell category are also Tap cells (anchor cells or hook cells). The primary purpose of a tap cell is to provide a low-resistance connection between the wells or substrate and the voltage supply line (VDD/VSS). Specifically, a tap cell is a non-logic cell that has a “well tie” and/or “substrate tie” built in.

• Tap cells are typically inserted into the cell row at regular intervals as specified by the design rules. This ensures that the local well voltage is always fixed to the source, preventing latch-up due to the formation of a shorted semiconductor path between VDD and GND. (Latch-up occurs when unwanted parasitic transistors turn on, creating a current from VDD to GND, resulting in complete damage to the IC.)

• Tap cells act as “runaway current guides” for the wells to keep the voltage inside the transistors correct, avoiding parasitic transistor activation. Typically, tap cells do not need to be placed behind each individual cell; instead, they are spaced appropriately to ensure voltage safety while also allowing for “bias” to be applied to each well or base to optimize performance and leakage.

• For example, in triple-well technologies, the N-well can be anchored to a voltage other than VDD, or the P-well base can be anchored to a voltage other than VSS, to control the transistor threshold. In short, tap cells are important because they ensure that the wells are well anchored, prevent latch-up, and stabilize the transistor threshold during operation.

• Engineering Change Order (ECO) Cells : is a late engineering change in the chip design process, typically made after the place-and-route step or even after the silicon has been taped out.

• The purpose of ECO is to fix minor bugs or add necessary features that arise near the end of the project, without having to remanufacture the entire chip mask.

• For example, when a change is discovered after the chip has been laid out, manufacturers often update the design by adding a few layers of metal (a technique called “metal-fixing”) rather than redesigning the entire design. To help with this, a number of ECO cells (also called spare cells or bonus cells) are often included in the chip layout. These cells initially have no function in the circuit (they do not appear in the logic netlist) but are pre-inserted into empty slots in the layout.

• When ECO is needed, engineers simply redesign the metal mask and via to connect the transistor pins of the ECO cells to each other or to the desired signal lines. Thanks to that, ECO cells can be quickly “loaded” with functions into basic logic gates such as AND, NAND, XOR, FF, MUX, ... or combine them to create more complex functions.

• For example, two NAND gate ECO cells can be connected to form an AND gate when needed. ASIC standard libraries typically define these ECO cells (with special names or symbols) so that the EDA tool can recognize them and keep them idle until they need to be “activated” with a new mask. With ECO cells, designers can fix or optimize logic signals with low cost (just adding a few layers of masks) without having to go back to the complex synthesis and placement/layout stages.

• Cell height: Measured by the number of “tracks” (pitch of M1). 

• For example, an 8-Track cell allows 8 horizontal M1 wires. More tracks means wider transistors, higher speed, but also larger area. 7-8 track height library is good for cross-section, 11-12 track is good for performance but high leakage, 9-10 track is average.

• Parameter example: Cell height = H (number of tracks), Power rail width W1, Vertical grid W2, Horizontal grid W3, N-Well height W4 (bottom table) shows the values.

• The .lib file has a hierarchical structure consisting of library, cell, pin, and timing groups. The first part (Library level) declares general information of the entire library such as operating conditions, units, wireload model, distribution lookup table, etc.

• For example, wire-load model parameters are often defined here. Each standard cell (cell) is described in a cell (cell_name) {...} block which includes general properties (function, area, …) and pin groups (pins). Each pin in the cell is declared in pin (pin_name) { … }, which defines the function, statics, as well as timing blocks to contain the arc-specific delay model.

• For example, each input-output arc is defined by timing arcs with attributes such as propagation delay (TPD), transition time (trise, tfall), input slew, etc.

• Thanks to this structure, the STA tool can quickly retrieve the delay and power of each component when analyzing the circuit; at the same time, the logic synthesizer also knows the basis for generating the appropriate netlist.

• To overcome the shortcomings of NLDM, nonlinear current source-based models are proposed, including CCS and ECSM.

• As shown in the figure, the CCS/ECSM model treats the output of the digital cell as a nonlinear current source circuit instead of an ideal voltage source. This allows the model to more accurately reflect the actual current changes when the switching input signal and load capacitance change. In CCS/ECSM, the controller is described as a nonlinear current source, and the receiver has a dynamically changing capacitance.

• The downside is that more data is needed (multiple lookup tables, even voltage wave data) and the calculations are a bit more complicated. In return, the accuracy increases greatly: as shown in the figure, CCS/ECSM achieves an error within 2% of the SPICE result and is a mandatory method for advanced nodes below 130nm.

• In summary, CCS/ECSM is used in the final design step (sign-off) for the most reliable delay and power consumption, while NLDM is mainly used in the earlier stages for speedup.