Introduction To Physical Design Flow

Physical Design Introduction

Before we dive into PD Flow, let’s first look at the inputs required for the PD process in this article.

Physical Design generates a layout format known as GDSII, which is then sent to the foundry for chip fabrication.

This is the process of converting the gate-level netlist into a layout. At each stage, various checks and validations are performed on the design, which involve different methods of analysis and verification. In this article, we will introduce the overall flow and details of each stage of Physical Design while sanity checks, analysis and verification will be covered in the subsequent articles.

The figure below illustrates the most basic Physical Design flow. 

However, there are some companies may have their own adjusted flows.

Floorplan

Floorplan is one the critical & important step in Physical design. Quality of your Chip / Design implementation depends on how good is the Floorplan. A good floorplan can be make implementation process (place, cts, route & timing closure) cake walk. On similar lines a bad floorplan can create all kind issues in the design (congestion, timing, noise, IR, routing issues). A bad floorplan will blow up the area, power & affects reliability, life of the IC and also it can increase overall IC cost (more effort to closure, more LVTs/ULVTs).

Floorplanning defines the following concepts:

• Determining shape of chip.

• Placing macros/ IP such as SRAM, PPL, etc

• Determining the core and die area.

• Creating the IO pad ring and PG Mesh (power delivery network).

Steps of Floorplan:

• Die size estimation.

• I/O port placement.

• Macro placement.

• Row creation.

• Placement blockages.

• Power planning.

• Adding physical only cells.

In general, a high-quality floorplan often requires many iterations. A good floorplan leads to minimize congestion and improves timing in the upcoming step. Once floorplan is done, we need to perform sanity checks before the placement stage.

Placement

In this stage, all the standard cells are placed in the design (size, shape & macro-placement is done in floorplan). Placement will be driven by different criteria like timing driven, congestion driven, power optimization etc. Timing & Routing convergence depends a lot on quality of placement.

Goals of Placement:

• Timing, Power and Area optimizations.

• Minimum congestion.

• Minimal cell density, pin density and congestion hot-spots.

• Minimal timing DRVs.

Steps of Placement:

• Pre-placement: There are few std cells which needs to be placed across the core area to meet the founder requirement. End-cap cells, tap-cells, I/O buffers, spare cells etc... are pre-placed cells.

• Coarse Placement: Initial fast placement of std cells without logical optimization.

• Placement Legalization: To avoid overlapping cells need to have legalized locations. Overlapping cells cannot be fabricated, creates shorts etc…

• High Fan-Out Nets (HFNs): All high fan-out nets will be synthesized (buffer tree) except clock nets. HFNs is the process of buffering the high fan-out nets to balance the load. Too many load affects delay numbers and transition times because load is directly proportional to the delay. By buffering the HFN the load can be balanced.

• Timing/Power Optimization: It includes cell sizing, cloning, buffer insertion, etc.

• Scan chain reordering: DFT tool flow makes a list of all the scan-able flops in the design, and sorts them based on their hierarchy. Scan-chain reordering helps to reduce congestion, total wire-length etc.

Clock Tree Synthesis (CTS)

Clock Tree Synthesis (CTS) is one of the most important stages in PnR. CTS QoR decides timing convergence & power. In most of the ICs clock consumes 30-40 % of total power. So efficient clock architecture, clock gating & clock tree implementation helps to reduce power.

The process of distributing the clock and balancing the load is called CTS. Basically, delivering the clock to all sequential elements. CTS is the process of insertion of buffers or inverters along the clock paths of ASIC design in order to achieve zero/minimum skew or balanced skew. Before CTS, all clock pins are driven by a single clock source. CTS starting point is clock source and CTS ending point is clock pins of sequential cells.

CTS Goals/Constraints:

• Max transition.

• Max capacitance.

• Max fanout.

CTS Flow:

• Read CTS SDC.

• Compile CTS using CTS spec file.

• Place clock tree cells.

• Route clock tree.

Routing

Making physical connections between signal pins using metal layers are called Routing. Routing is the stage after CTS and optimization where exact paths for the interconnection of standard cells and macros and I/O pins are determined. Electrical connections using metals and vias are created in the layout, defined by the logical connections present in the netlist (i.e. Logical connectivity converted as physical connectivity).

After CTS, we have information of all the placed cells, blockages, clock tree buffers/inverters and I/O pins. The tool relies on this information to electrically complete all connections defined in the netlist such that:

• There are minimal DRC violations while routing.

• The design is 100% routed with minimal LVS violations.

• There are minimal SI related violation.

• There must be no or minimal congestion hot spots.

• The Timing DRCs & QoR are met and good respectively.

Goals of Routing:

• Minimize the total interconnect/wire length.

• Minimize the critical path delay.

• Minimize the number of layer changes that the connections have to make (minimizing the number vias).

• Complete the connections without increasing the total area of the block.

• Meeting the Timing DRCs and obtaining a good Timing QoR.

• Minimizing the congestion hotspots.

• SI driven: reduction in cross-talk noise and delta delays.

Sign-Off

Once routing is done we need to insert filler cells followed by metal fill and then power signoff, timing signoff, and physical verification. Once all these steps are done in final we stream out the layout in the form of GDSII or OASIS file which is called tapeout. A detail discussion on each stage will be on coming articles.

Important concepts of Sign-Off:

• Crosstalk.

• Crosstalk Noise.

• Crosstalk Delay.

• Antenna Effect.

• IR Drop Analysis.

• EM.