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Timing is the timing regulations that digital circuits must comply with and meet when being synthesized and laid out. Timing is one of the important factors that must always be considered and evaluated when synthesizing and laying out digital circuits. Synthesis software such as Design Compiler will perform static timing analysis to select appropriate logic gates to create netlists. Layout software such as IC compiler will base on the results of static timing analysis to place cells and route the cells to create a layout. Timing analysis software such as Prime Time will check the timing of the entire design at the desired clock speed. This article will provide an overview of some concepts in static timing analysis.
What is STA ?
What is STA ?
Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.
Another way to perform timing analysis is to use dynamic simulation, which determines the full behavior of the circuit for a given set of input stimulus vectors. Compared to dynamic simulation, static timing analysis is much faster because it is not necessary to simulate the logical operation of the circuit. STA is also more thorough because it checks all timing paths, not just the logical conditions that are sensitized by a set of test vectors. However, STA can only check the timing, not the functionality, of a circuit design.
Compared with digital circuit simulation, timing analysis is performed faster and more comprehensively.
Faster because timing analysis does not require the use of as many different test vectors as functional simulation. Test vectors are the design input values that the simulator will construct to test the design functionality.
More comprehensive because it checks the worst-case timing for all possible logical conditions rather than being limited to a fixed set of test vectors. However, static timing analysis only checks the timing properties of the design, not the functional correctness of the design.
Timing, area, and power constraints are three factors that affect the synthesis and physical design (layout) of digital circuits. Synthesis and layout software always aim to make the created microchip have the fastest operating speed, smallest area, and least power consumption to suit the design requirements. This software will find a way to balance the speed, area, and power factors of the design and the running time of the software based on the constraints (settings) of the designer. However, a chip must satisfy timing constraints to be able to process correctly at a desired clock speed. Timing is the most important constraint of the design. Large area or high power still ensures the function of the chip, but incorrect timing will cause the chip to function incorrectly.
Static timing analysis is to answer the question "When the positive edge (rising or falling edge) of the clock appears, does a correct data always appear at the input of a synchronous cell, such as a Flip-Flop (FF), under all operating conditions?". In this question, we see that timing analysis is associated with a clock definition. The input value of a synchronous cell can change during the operation of the chip, timing testing is to ensure that a synchronous cell always captures the correct input data.
Take a simple example as follows so you can visualize timing, a bus company has a daily departure schedule from Ho Chi Minh City to Bao Loc City, 1 trip every hour, passengers must be present before or at the times of 6 o'clock, 7 o'clock, 8 o'clock, ... for the bus to run. In addition, the bus company recommends that passengers arrive 15 minutes before the trip, this is like a timing constraint, if the passenger arrives 15 minutes before, they can always get on the desired bus. A passenger wants to take the bus at 8 o'clock, if this passenger arrives before or exactly at 7:45, he can get on the desired bus, this corresponds to the timing being satisfied, called MET timing. If this passenger arrives after 7:45, the passenger may be late for the bus, this corresponds to the timing being violated, called VIOLATED timing. Here, the schedule of 1 trip every hour is like a clock pulse. This example is only used to help you visualize the concept of timing, but in reality, timing analysis in microcircuit design is not that simple.
Static vs Dynamic
Static vs Dynamic
The STA is static since the analysis of the design is carried out statically and does not depend upon the data values being applied at the input pins.
This is in contrast to simulation based timing analysis where applying input vectors and resulting behavior is observed and verified.
=> provides a faster and simpler way of checking and analyzing all the timing paths in a design for any timing violations.
How does STA works
How does STA works
When performing timing analysis, STA first breaks down the design into timing paths. Each timing path consists of the following elements:
Startpoint: The start of a timing path where data is launched by a clock edge or where the data must be available at a specific time. Every startpoint must be either an input port or a register clock pin.
Combinational logic network: Elements that have no memory or internal state. Combinational logic can contain AND, OR, XOR, and inverter elements, but cannot contain flip-flops, latches, registers, or RAM.
Endpoint: The end of a timing path where data is captured by a clock edge or where the data must be available at a specific time. Every endpoint must be either a register data input pin or an output port.
The following figure shows the timing paths in a simple design example:
A combinational logic cloud might contain multiple paths, as shown in the following figure. STA uses the longest path to calculate a maximum delay and the shortest path to calculate a minimum delay.
STA also considers the following types of paths for timing analysis:
Clock path: A path from a clock input port or cell pin, through one or more buffers or inverters, to the clock pin of a sequential element; for data setup and hold checks.
Clock-gating path: A path from an input port to a clock-gating element; for clock-gating setup and hold checks.
Asynchronous path: A path from an input port to an asynchronous set or clear pin of a sequential element; for recovery and removal checks.
After breaking down a design into a set of timing paths, an STA tool calculates the delay along each path. The total delay of a path is the sum of all cell and net delays in the path.
Cell delay is the amount of delay from input to output of a logic gate in a path. In the absence of back-annotated delay information from an SDF file, the tool calculates the cell delay from delay tables provided in the logic library for the cell.
Typically, a delay table lists the amount of delay as a function of one or more variables, such as input transition time and output load capacitance. From these table entries, the tool calculates each cell delay.
Net delay is the amount of delay from the output of a cell to the input of the next cell in a timing path. This delay is caused by the parasitic capacitance of the interconnection between the two cells, combined with net resistance and the limited drive strength of the cell driving the net.
STA then checks for violations of timing constraints, such as setup and hold constraints:
A setup constraint specifies how much time is necessary for data to be available at the input of a sequential device before the clock edge that captures the data in the device. This constraint enforces a maximum delay on the data path relative to the clock edge.
A hold constraint specifies how much time is necessary for data to be stable at the input of a sequential device after the clock edge that captures the data in the device. This constraint enforces a minimum delay on the data path relative to the clock edge.
The following example shows how STA checks setup and hold constraints for a flip-flop: (setup and hold check will be in Timing Concepts and Timing Reports sections).
For this example, assume that the flip-flops are defined in the logic library to have a minimum setup time of 1.0 time units and a minimum hold time of 0.0 time units. The clock period is defined in the tool to be 10 time units. The time unit size, such as ns or ps, is specified in the logic library.
By default, the tool assumes that signals are propagated through each data path in one clock cycle. Therefore, when the tool performs a setup check, it verifies that the data launched from FF1 reaches FF2 within one clock cycle, and arrives at least 1.0 time unit before the data gets captured by the next clock edge at FF2. If the data path delay is too long, it is reported as a timing violation. For this setup check, the tool considers the longest possible delay along the data path and the shortest possible delay along the clock path between FF1 and FF2.
When the tool performs a hold check, it verifies that the data launched from FF1 reaches FF2 no sooner than the capture clock edge for the previous clock cycle. This check ensures that the data already existing at the input of FF2 remains stable long enough after the clock edge that captures data for the previous cycle. For this hold check, the tool considers the shortest possible delay along the data path and the longest possible delay along the clock path between FF1 and FF2. A hold violation can occur if the clock path has a long delay.
If certain paths are not intended to operate according to the default setup and hold behavior assumed by the STA tool, you need to specify those paths as timing exceptions. Otherwise, the tool might incorrectly report those paths as having timing violations.
An STA tool may let you specify the following types of exceptions:
False path: A path that is never sensitized due to the logic configuration, expected data sequence, or operating mode.
Multicycle path: A path designed to take more than one clock cycle from launch to capture.
Minimum or maximum delay path: A path that must meet a delay constraint that you explicitly specify as a time value.
What tool is used for STA ?
What tool is used for STA ?
Synopsys' PrimeTime static timing analysis tool provides a single, golden, trusted signoff solution for timing, signal integrity, power and variation-aware analysis. The Synopsys PrimeTime suite includes: PrimeTime, PrimeTime SI, PrimeTime ADV, and PrimeTime PX. It delivers HSPICE® accurate signoff analysis which helps pinpoint problems prior to tapeout, thereby reducing schedule risk, ensuring design integrity, and lowering the cost of design.
This industry gold-standard solution improves your team’s productivity by delivering fast turnaround on development schedules for large and small designs while ensuring first-pass silicon success through greater predictability and the highest accuracy.
The Cadence Tempus Timing Solution is the industry’s most trusted static timing analysis (STA) tool for FinFET designs. It is the fastest STA tool in the industry, providing faster design closure turnaround time while delivering the best-in-its-class power, performance, and area (PPA). Customers trust innovative Tempus capabilities such as SmartScope, CMMMC, Design Robustness Analysis (DRA) Suite, SmartMMMC Optimization, etc. to optimize and signoff their most complex, large, and complicated designs at advanced nodes.
The Tempus solution is deeply integrated with Cadence’s Innovus Implementation System, Quantus Extraction Solution, and Voltus IC Power Solution to deliver the best user experience during the entire design cycle.
References
References
https://nguyenquanicd.blogspot.com/2018/07/sta-tong-quan-ve-phan-tich-timing-tinh.html
https://www.synopsys.com/glossary/what-is-static-timing-analysis.html
Static Timing Analysis for Nanometer Designs by J. Bhasker • Rakesh Chadha
Timing Analysis by Dr. Adam Teman
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