Сombinational and sequential logic

You: the topic of conversation is schematics

Losh@dka: 3 Synchronous and Asynchronous Circuits In theory, due to the lack of time constraints imposed on the system by clocked registers, the designer has more freedom when designing asynchronous circuits than when designing synchronous ones. In the same way that analog circuits are less formalized than digital ones, due to the fact that arbitrary voltages can be used in analog circuits, asynchronous circuits are less formalized than synchronous ones, since they can have any feedback. However, it turns out that synchronous circuits are easier to design and use than asynchronous circuits, just as digital circuits are easier to design than analog ones. Despite years of scientific research into asynchronous circuits, almost all modern digital circuits are synchronous. Asynchronous circuits are sometimes used to communicate between systems with different clock signals or to read values ​​from inputs at any time, just as analog circuits are needed to interact with the real world of analog (continuous) voltages.

The rules for combinational composition tell us how we can construct a large combinational circuit from smaller combinational elements. A circuit is combinational if it consists of interconnected elements and the following conditions are met: „Each circuit element is itself combinational; „Each connection of the circuit is either an input, or is connected to a single output of another circuit element; “The diagram does not contain cyclic paths: each path in the diagram goes through any connection at most once. The rules for combinational composition of circuits are sufficient, but not strictly necessary. Some circuits that do not obey these rules are still combinational, since the values ​​of their outputs depend only on the current values ​​at the inputs. However, it can be quite difficult to determine whether some atypical circuits are combinational or not, therefore, when developing combinational circuits, we usually limit ourselves to the rules of combinational composition.

Modern synthesis tools build schematic diagrams for the implementation of these functions, and a scrupulous developer analyzes these diagrams, as well as any warnings that appear during the synthesis process, to make sure that the desired logic is implemented. Sometimes a sloppy description leads to the generation of circuits that are larger than required, and circuits with asynchronous logic. When the synthesis results are satisfactory, the development environment maps the functions to the logic gates of a specific microcircuit. The Placement and Trace tool determines which conversion table each function belongs to and how these tables are connected. The propagation delay of the signal increases with the length of the conductor, so the most critical circuits should be placed as close to each other as possible.

You: how to construct equations of Boolean logic from states and transitions between states?

Losh@dka: We will often use the terms "current state" and "next state" to distinguish the state of the system in the present from the state of the system to which it will transition on the edge of the next clock pulse. The functional description defines the next state and meaning of each output for every possible combination of current states and input signals. The time specification consists of the upper limit tpcq and the lower limit tccq of the duration of the time interval from the leading edge of the clock pulse to the moment the output signal changes, as well as the preset and hold times tsetup and thold, which determine the time interval before and after the arrival of the clock pulse edge, during which the values ​​at the inputs should not change. tpcq is the propagation delay of the clock input - output Q path (until the new value is fully set) of the sequential logic. tccq is the response delay of the clock input - output Q path.: ~)

Then, for all states of the machine, you need to choose an encoding and, based on the diagram, create a table of transitions between states and a table of outputs, which show the next state and output signal for a given current state and input signal. From these tables, the combinational logic is designed, which determines the next state and output, and a schematic is drawn. Synchronous sequential circuits have a timing specification that includes the propagation and response delays of the clock I / O path, tpcq and tccq, as well as preset and hold times, tsetup and thold. For such circuits to work correctly, their inputs must be stable during the aperture time, which consists of the preset time before the leading edge of the clock pulse and the hold time after it. The minimum system clock period Tc is equal to the sum of the combinational logic propagation delays, tpd, and the tpcq + tsetup register delays.

Chapter 2 will also show you how you can design a circuit with multiple logic gates so that all the possible states of the circuit correspond to the states previously described in the truth table or using the Boolean logic equation. Chapter 3 describes sequential logic. Such logic already assumes that the result at the output of a logic gate depends on both the current state of the input and its past states. The Register is the most common piece of sequential logic that “remembers” the previous state at its input. Finite state machines, built on the basis of registers and combinatorial logic, are powerful tools for building complex systems on a system basis. ; -E

You: how a combinational circuit of logic gates is built using a state machine, say a few more words

Losh@dka: The rules of combinational composition tell us how we can construct a large combinational circuit from smaller combinational elements. A circuit is combinational if it consists of interconnected elements and the following conditions are met: „Each circuit element is itself combinational; „Each connection of the circuit is either an input, or is connected to a single output of another circuit element; “The diagram does not contain cyclic paths: each path in the diagram goes through any connection at most once. The rules for combinational composition of circuits are sufficient, but not strictly necessary. Some circuits that do not obey these rules are still combinational, since the values ​​of their outputs depend only on the current values ​​at the inputs. However, it can be quite difficult to determine whether some atypical circuits are combinational or not, therefore, when developing combinational circuits, we usually limit ourselves to the rules of combinational composition.

The choice of VDD and logic levels can be arbitrary, but this choice must ensure the compatibility of all logic gates exchanging data within one digital system. Therefore, gates are usually grouped into logic families in such a way that any element from one family, when combined with any other element from the same family, automatically enforces the principle of static discipline. Logic gates of the same family connect to each other as easily as Lego blocks, because they are fully compatible in power supply voltage and logic levels. Four main families of logic gates dominated from the 70s to the 90s of the last century - TTL - Transistor-Transistor Logic (TTL), CMOS - logic built on a complementary structure of metal-oxide-semiconductor (Complementary Metal-Oxide-Semiconductor Logic, or CMOS), NTTL - Low-Voltage Transistor-Transistor Logic (LVTTL), and Low-Voltage Complementary Metal-Oxide - Semiconductor Logic, or LVCMOS). Logic levels for all these families are presented in Tab. : - {

You: what is static discipline?

Losh@dka: The portion of the sequence element's aperture time before the edge of the clock pulse is called the setup time, after the edge it is called the hold time. Like static discipline, which only allows logic levels to be used outside the restricted area, dynamic discipline only allows signals that change outside of aperture time. When fulfilling the requirements of dynamic discipline, we can operate with discrete units of time, which are called clock cycles, in the same way as we operate with discrete logic levels 1 and 0. A signal can change and oscillate for a certain limited period of time. When fulfilling the requirements of dynamic discipline, only its value at the end of the clock cycle, when it has already reached a stable value, is important. ; -}

Because of the need to perform periodic refresh and post-read refresh, DRAM has less bandwidth than static RAM. Modern varieties of DRAM, such as Synchronous Dynamic RAM (SDRAM) and Double Data Rate Synchronous DRAM (DDR SDRAM, or DDR for short), have been developed to overcome this problem. Synchronous DRAM uses a clock signal to pipe the memory access. In double-rate SDRAM, data is transferred on both the rising and falling edges of the clock, which doubles the bandwidth at a given clock frequency. Double Rate Synchronous DRAM was first standardized in 2000 and operated at frequencies from 100 to 200 MHz.

However, if VIL rises, VOH falls almost vertically. Logic gates should be designed in accordance with the principle of static discipline to avoid input signals into restricted areas. The principle of static discipline requires that, provided that there are logically correct signals at the input, each element of the system produces logically correct signals at the output.

You: please tell us about dynamic discipline

Losh@dka: Transfer characteristics and noise levels Applying the principle of static discipline limits the designer's freedom in choosing analog elements for building digital systems, but helps to ensure the simplicity and reliability of the designed digital circuits. Using this principle, the designer rises from the analog level of abstraction to the digital level, which increases the designer's productivity by eliminating unnecessary detail. The choice of VDD and logic levels can be arbitrary, but this choice must ensure the compatibility of all logic gates exchanging data within one digital system. Therefore, gates are usually grouped into logic families in such a way that any element from one family, when combined with any other element from the same family, automatically enforces the principle of static discipline. Logic gates of the same family connect to each other as easily as Lego blocks, because they are fully compatible in power supply voltage and logic levels.

You: Major Time Periods in a Dynamic Discipline

Losh@dka: The portion of the sequence element's aperture time before the edge of the clock pulse is called the setup time, after the edge it is called the hold time. Like static discipline, which only allows logic levels to be used outside the restricted area, dynamic discipline only allows signals that change outside of aperture time. When fulfilling the requirements of dynamic discipline, we can operate with discrete units of time, which are called clock cycles, in the same way as we operate with discrete logic levels 1 and 0. A signal can change and oscillate for a certain limited period of time. When fulfilling the requirements of dynamic discipline, only its value at the end of the clock cycle, when it has already reached a stable value, is important.

Timing specification of synchronous sequential circuit. After the 0 → 1 transition of the clock signal (the leading edge of the clock pulse), the output (or outputs) of the circuit can begin to change no earlier than after tccq time (clock-to-Q response delay, contamination delay clock-to-Q3), and must accept stationary value no later than tpcq (propagation delay clock-to-Q). These values ​​represent the smallest and largest delays of the circuit, respectively. (or inputs) of the circuit must be stable for some setup time tsetup before the rising edge of the clock, and should not change for the hold time thold after the rising edge of the clock. The sum of the preset and hold times is called aperture time circuit, this is the total time during which the information input signal must be stable for its fixation at the output. Dynamic discipline requires that Both inputs of the synchronous sequential circuit were stable for the preset time before and the hold time after the clock edge.

You: thanks, the basics of sequential circuits are clear, say a few words in the end to a novice circuit designer?

Losh@dka: They are simple sequential circuits that store one bit of information. Generally speaking, sequential circuits are difficult to analyze. In order to simplify the design, we will restrict ourselves only to synchronous circuits consisting of combinational logic and a set of triggers storing information about the state of the system. This chapter describes finite state machines with which you can easily and easily design sequential circuits. Finally, we analyze the performance of sequential circuits and discuss parallel computing as a way to improve performance.

34, a shift register can be constructed from N flip-flops connected in series. Some shift registers have a reset signal to initialize all flip-flops. A parallel-to-serial converter is loaded in parallel with N bits, which are then sequentially (one bits at a time) sent to the output. The circuitry of a parallel-to-serial converter and a shift register is similar. The shift register can be modified to perform both serial-to-parallel and parallel-to-serial conversion by adding the parallel input DN − 1: 0 and the Load control signal, as shown in Fig. five. ;-}

In this chapter, we will analyze and design sequential logic circuits. The output value of sequential logic depends on both the current and previous input values, hence sequential logic has memory. Sequential logic circuits can explicitly remember the previous values ​​of certain inputs, or they can "compress" the previous values ​​of certain inputs into less information, called the system state. The state of a digital sequential circuit is a set of bits called state variables.