Logic linear and physical addresses

You: the topic of conversation is memory organization

Losh@dka: Various memory technologies such as SRAM, DRAM, and hard drives offer a trade-off between capacity, speed and memory cost. In this chapter, we looked at the organization of the memory hierarchy, including cache memory and virtual memory, that allows developers to get closer to the ideal of large, fast, and cheap memory. Random access memory usually uses dynamic memory (DRAM) and is significantly slower than the processor. The cache, which stores frequently accessed data in much faster static SRAM, is used to reduce memory access times. Virtual memory allows you to increase the amount of available memory by using a hard disk that contains data that does not fit into the RAM Chapter 8 Memory Hierarchy and I / O Subsystem 1387 memory. ; -}

HDD. The goal of incorporating a hard disk into a memory hierarchy is to inexpensively create the appearance of large memory, while still providing access rates for most memory accesses equal to those of faster memory types. For example, a computer with 128 MB of RAM can provide the appearance of 2 GB of RAM by using a hard drive. In this case, the large memory, 2GB, is called virtual memory, and the smaller memory, 128MB, is called physical memory. In this section, we will use the term physical memory to mean random access memory.

But processor speed grew faster than memory speed. Currently, DRAM (Dynamic Random Access Memory) is 10 to 100 times slower than a processor. The widening gap in speed between the processor and RAM requires more and more sophisticated memory subsystems to try to bring the memory speed closer to the processor's speed. The first half of this chapter focuses on memory subsystems and analyzes the various trade-offs between speed, capacity, and cost. The processor works with memory through the memory interface. ; -}

Fast memory is used to store frequently used data and instructions, so it seems that the memory subsystem is always pretty fast. The rest of the data and instructions are stored in large memory, which is slower, but allows for a large total memory. A combination of two cheap memory types is a much less expensive option than one large and fast memory. This principle applies to the entire memory hierarchy, since as the amount of memory increases, its speed decreases. A computer's RAM is usually built on dynamic memory (DRAM) chips. ;-)

You: tell me about memory organization in Windows?

Losh@dka: Cluster built before recording. Finally, the page fault handler uses information from the reservation bitmap and PTE records to determine the start and end points of the clusters to efficiently load the required pages. Physical memory limits. Now that you've learned how Windows monitors physical memory, let's talk about how much of that memory Windows can actually support. Since most systems in the course of their work access code and data that exceeds the capacity of physical memory, this memory is essentially a window for accessing the used code and data. The amount of memory can thus affect performance; when the data (or code) that a process or operating system needs is not available, the memory manager must bring it into memory from disk or from remote storage. In addition to the impact on performance, the amount of physical memory determines the limits of other resources. For example, it is quite obvious that the volumes of the non-paged pool, operating system buffers supported by physical memory, are limited by the amount of this memory.

You: what memory models does the x86 processor support?

Losh@dka: In this case, reading from the cache will still occur

bit 29: NW - disables write-through to the internal cache - data written to the cache does not appear on the external pins of the processor

bit 18: AM - allows the AC flag to enable a mode in which unaligned memory accesses at privilege level 3 cause the # AC exception

bit 16: WP - prohibits writing to pages marked as "read-only" at all privilege levels (if WP = 0, protection applies only to level 3). This bit is intended to implement the process copying method, popular in UNIX, in which all the memory of the new process first completely coincides with the old one, and then, when trying to write, a copy of the page that is being accessed is created.

bit 5: NE - enables the mode in which FPU errors cause exception #MF, not IRQ13

bit 4: ET - used only on 80386DX and indicated that FPU is present

bit 3: TS - set by the processor after switching tasks. If you then execute any FPU command, exception #NM will occur, the handler of which can save / restore the FPU state, clear this bit with the CLTS command and continue the program.

bit 2: EM - coprocessor emulation. Each FPU command raises #NM exception

bit 1: MP - Controls how the WAIT command is executed. Must be installed for compatibility with programs written for 80286 and 80386 and using this command

bit 0: PE - if it is equal to 1, the processor is in a protected mode (the rest of the bits are reserved, and programs should not change their values)

CR1: reserved

CR2: page error address register. When a #PF exception occurs, the linear address that caused the exception can be read from this register.

CR3 (PDBR): Main Page Table Register

bits 31-11: 20 most significant bits of the physical address of the start of the page directory if bit PAE in CR4 is zero, or bits 31-5: 27 most significant bits of the physical address of the table of pointers to page directories if bit PAE = 1 bit 4

(80486+): PCD bit (disable page caching) - this bit prohibits loading the current page into the cache memory (for example, if an interrupt has occurred and the system does not want the interrupt handler to evict the main program from the cache), bit 3

(80486+): PWT (Page Write-Through) bit - Controls the method of writing pages to the external cache

CR4: This register (introduced only in Pentium processors) controls new processor capabilities.

You: linear memory model

Losh@dka: You can see how much of the installed RAM the operating system sees in the System Properties dialog box, but to find out how much memory is actually available to Windows, you need to open the Performance tab of the Task Manager or use the utilities Msinfo32 and Winver. As shown by the Msinfo32 utility, on one particular laptop with 4GB of RAM and 32-bit Windows 10 installed, the amount of available physical memory was 3.87GB. Installed random access memory (RAM) 4.0 GB; total physical memory 3, 8 7 GB. The physical memory structure can be viewed using the Memlnfo program. Below is the result of running the Memlnfo utility on a 32-bit system with the -r switch, designed to dump physical memory ranges: C: \ Tools> MemInfo. exe -r

You: memory segments and their selectors

Service functions provided by the memory manager The memory manager provides a set of service functions for allocating and freeing virtual memory, sharing memory between processes, mapping files to memory, writing virtual pages to disk, getting information about a range of virtual pages, changing virtual page protection and locking virtual pages in memory. The memory management service functions, like other Windows runtime services, allow the caller to pass a process descriptor to designate the specific process you intend to work with in virtual memory. The caller can work either with its own memory, or (with the necessary permissions) with the memory of another process. For example, if a process creates a child process, by default it is granted the right to work with the virtual memory of the child process.

To get a linear address from a boolean, the processor adds to the offset the linear address of the segment start, which is stored in the base field in the segment descriptor. A segment descriptor is an 8-byte data structure located in a GDT or LDT; the address of the table is in the GDTR or LDTR register, and the descriptor number in the table is determined by the value of the selector. The descriptor for the selector located in the segment register is not read from memory with each access, but is stored in a hidden part of the segment register and is loaded only when the MOV (to the segment register), POP (to the segment register), LDS, LES, LSS commands are executed. LGS, LFS and long distance jump commands. A selector is a 16-bit number in the following format:

bits 16-3: table descriptor number (0 to 8191)

bit 2: 1 - use LDT, 0 - use GDT

bits 1-0: the requested privilege level when accessing the segment and the current privilege level for the selector loaded in CS

A selector containing bits zero 16-3 is called zero and is required to load unused segment registers. ;-)

You: translating a linear address to a page address in a page table

Losh@dka: Address translation using page table. The page table can be stored anywhere in physical memory, its location is determined by the operating system. The processor usually uses a dedicated register called the page table register to store its base address. To perform a load or save operation, the processor must first translate the virtual address to the physical one and then access the physical memory using the obtained physical address. The processor extracts the virtual page number from the virtual address and appends it to the contents of the page table register to find the physical address of the corresponding entry in the page table located in physical memory. The processor then reads this record and gets the physical page number.

You: thanks for the interview, Losh@dka!