You: the topic of conversation - registers, triggers and latches

Losh@dka: The exception reason and EPC registers are part of Coprocessor 0 - the part of the MIPS processor that performs system functions. Coprocessor 0 can contain up to 32 special-purpose registers, including the exception reason and EPC registers. The exception handler can use the mfc0 instruction (read from Coprocessor 0) to copy these special-purpose registers to one of the general-purpose registers in the register file; inside Coprocessor 0, the exception reason register is located at number 13, and the EPC at number 14. In order to handle exceptions, we must add the exception reason and EPC registers to the data path and extend the PCSrc multiplexer so that we can also select the address of the exception handler as shown in Fig. : -]

Sample code. FUNCTION PRESERVING PROTECTED REGISTERS ON THE STACK. MIPS assembly code:

addi $sp, $sp, −4 # make space on stack to store one register

sw $s0, 0 ($sp) # save $ s0 on stack

add $t0, $a0, $a1 # $ t0 = f + g

add $t1, $a2, $a3 # $ t1 = h + i

sub $s0, $t0, $t1 # result = (f + g) - (h + i)

add $v0, $s0, $0 # put return value in $ v0

lw $s0, 0 ($sp) # restore $ s0 from stack

addi $sp, $sp, 4 # deallocate stack space

jr $ra # return to caller

Recall that when one function calls another, the first is called the calling function and the second is called the called. The called function must save and restore any guarded registers it intends to use, but is free to modify any non-guarded registers. Therefore, if the caller is keeping data up to date in non-preserving registers, it must preserve the non-preserving registers before calling another function and then restoring it. For this reason, shielded registers are also called invoked-retained registers, and non-retained registers are called caller-retained.

You: how the register and its circuit are implemented on logic gates and transistors?

Losh@dka: General form of an inverting logic gate. NMOS transistors transfer 0 well, so a pull-down network made up of such transistors is placed between the output pin and GND to transfer 0 to the output. P-MOS transistors transfer 1 well, so a pull-up network made up of such transistors is placed between the output pin and the supply voltage VDD to transfer 1 to the output. The buck and boost circuits can consist of transistors connected in parallel or in series. Moreover, when the transistors are connected in parallel, the entire circuit is turned on if at least one of the transistors is turned on.

When using pseudo-nMOS logic (pseudo-nMOS logic), or simply pseudo-logic, the slow stack of p-MOS transistors is replaced with one "weak" p-MOS transistor, which is always on. Such a transistor is often referred to as a weak pull-up transistor. The physical parameters of the p-MOS transistor are selected in such a way that this transistor to a high logic level (1) the output Y "pulls up weakly" - that is, only when all n-MOS transistors are turned off. But if at the same time at least one of the n-MOS transistors turns on, then, surpassing the weak pull-up transistor in power, it "pulls" the Y output so close to the GND ground voltage that the output is a logic 0.

You: register logic

Losh@dka: The destination operand is denoted as D (register or memory location) and the source operand is denoted as S (register, immediate operand, or memory location). Some x86 instructions:

ADD / SUB Add / Subtract D = D + S / D = D - S

ADDC Addition with carry D = D + S + CF

INC / DEC Increase / Decrease D = D + 1 / D = D - 1

CMP Compare Set flags based on D - S results

NEG Inverse D = −D

AND / OR / XOR Logical AND / OR / EXCLUSIVE OR D = D operation S

NOT Logical NOT D = D¯

IMUL / MUL Signed / unsigned multiplication EDX: EAX = EAX × D

IDIV / DIV Signed / unsigned division EDX: EAX / D EAX = quotient; EDX = remainder

SAR / SHR Arithmetic / Logical Shift Right D = D >>> S / D = D >> S

SAL / SHL Left shift D = D << S

ROR / ROL Cyclic shift right / left Cyclic shift D by S digits

RCR / RCL Cyclic shift right / left through carry bit Cyclic shift CF and D by S bits

BT Check bit CF = D [S] (bit number S of D)

BTR / BTS Check bit and reset / set it CF = D [S]; D [S] = 0/1

TEST Set flags based on bit test results Set flags based on D AND S results

MOV Copy operand D = S

PUSH Put on the stack ESP = ESP −4; Mem [ESP] = S

POP Read from stack D = MEM [ESP]; ESP = ESP + 4

CLC, STC Clear / set carry flag CF = 0/1

JMP Unconditional jump Jump to relative address: EIP = EIP + S Jump to absolute address: EIP = S

Jcc Branching (conditional branch) If the flag is set, then EIP = EIP + S

LOOP Checking the loop condition ECX = ECX - 1 If ECX ≠ 0, then EIP = EIP + imm

CALL Function call ESP = ESP - 4; MEM [ESP] = EIP; EIP = S

RET Return from function EIP = MEM [ESP]; ESP = ESP + 4

Please note that some commands always only operate on certain registers. For example, multiplication of two 32-bit numbers always uses EAX as one of the sources and always writes the 64-bit result to EDX and EAX.

Translation of an address using a page table. The page table can be stored anywhere in physical memory, its location is determined by the operating system. The processor usually uses a dedicated register called the page table register to store its base address. To perform a load or save operation, the processor must first translate a virtual address into a physical one, and then access physical memory using the obtained physical address. The processor extracts the virtual page number from the virtual address and appends it to the contents of the page table register to find the physical address of the corresponding entry in the page table located in physical memory. The processor then reads this record and gets the physical page number. :-)

You: trigger circuit

Losh@dka: D flip-flop is also known as MS flip-flop, master-slave flip-flop and edge-sync flip-flop. A triangle in the designation indicates that the input is edge synchronized. Many flip-flops do not have a Q¯ output and are usually used when Q¯ is not needed. Example 3. 1 NUMBER OF TRANSISTORS IN A TRIGGER How many transistors are there in the D-flip-flop described in this chapter? Solution: 4 transistors are used in the OR-NOT or AND-NOT element.

Trigger with reset function. The reset flip-flop adds another input called RESET. When RESET is 0, the resettable flip-flop behaves like a normal D flip-flop. When RESET is 1, such a flip-flop ignores input D and resets the output to 0. Reset triggers are useful when we want to speed up the establishment of a certain state. ; - {

Synchronously resettable flip-flop: (a) circuit, (b, c) designations Fig. 3. 11 (a) shows how to build a synchronously resettable flip-flop from a conventional D-flip-flop and an AND gate. When a logical zero arrives at RESET, the AND gate feeds 0 to the trigger input. When a logical unit comes to RESET, the AND gate passes the D signal to the trigger input.

You: register is made up of triggers?

Losh@dka: τ is a time constant that shows how quickly the trigger leaves the metastable state; it is related to the delay in the cross-connected flip-flop gates. Thus, if the input of a bistable device, such as a flip-flop, changes during the aperture time, its output may be in a metastable state for some time before going to a stable state of 0 or 1. The transition time to a stable state is not limited, because for any finite time t, the probability that the trigger is still in a metastable state is not zero. However, this probability falls off exponentially with increasing t. Therefore, if you wait long enough, much more than tpcq, then with a very high probability you can expect that the trigger will reach the correct logical state.

If the control device receives an undefined command (a command that you do not know how to execute), then it transitions to state S12, stores the command counter in the EPC register, writes 0x28 to the exception reason register, and performs an unconditional transition to the exception handler. Likewise, when an arithmetic overflow is detected in the add or sub commands, the control device transitions to state S13, stores the command counter in the EPC register, writes 0x30 to the exception reason register, and transfers control to the exception handler. Note that when an exception occurs, the command is aborted and nothing is written to the register file. When the processor decrypted the next command and realized that it was mfc0, it goes into the S14 state and writes the corresponding register of Coprocessor 0 to the register file. :-)

You: what is a latch?

Losh@dka: This is called a read after write (RAW) conflict. The add command writes the result to $s0 in the first part of the fifth measure, but the and command reads $s0 in the third measure, so it gets the wrong value. The or command reads $s0 in the fourth clock cycle, and also gets the wrong value. The sub command reads $ s0 in the second half of the fifth bar, that is, it finally gets the correct value that was written to the register in the first half of the fifth bar. All subsequent commands will also read the correct value from $s0. : -E

In this case, the command execution time means the number of clock cycles after which the next command can be launched for execution. If the command is executed in one cycle, then the command following it can be started already on the next cycle). Data load instructions are executed in one clock cycle if there are no conflicts, and in two clock cycles if the pipeline must be suspended to resolve the conflict, so their CPI = (0.6) (1) + (0.4) (2) = 1 ,4. Conditional branch instructions are executed in one clock cycle if the branch is predicted correctly, and in two clock cycles otherwise, so their CPI = (0.75) (1) + (0.25) (2) = 1.25. For unconditional jump commands, the CPI is always two. ; -}

You: clear, registers and command circuits are triggered on the leading edge of the clock pulse and are built on triggers

Losh@dka: Timing specification of a synchronous sequential circuit. After the 0 → 1 transition of the clock signal (the leading edge of the clock pulse), the output (or outputs) of the circuit can begin to change no earlier than after tccq time (clock-to-Q response delay, contamination delay clock-to-Q3), and must accept a stationary value no later than tpcq (propagation delay clock-to-Q). These values ​​represent the smallest and largest circuit delays, respectively. In order for the fixation to be performed correctly, the information input (or inputs) of the circuit must be stable for some setup time tsetup before the rising edge of the clock, and should not change for the hold time thold after the rising edge of the clock. The sum of the preset and hold times is called aperture time circuit, this is the total time during which the information input signal must be stable for its fixation at the output.Dynamic discipline requires that Both synchronous sequential inputs were stable for the preset time before and the hold time after the clock edge. : - {

We will often use the terms "current state" and "next state" in order to distinguish the state of the system in the present from the state of the system into which it will transition on the edge of the next clock pulse. The functional description defines the next state and meaning of each output for every possible combination of current states and input signals. The time specification consists of the upper limit tpcq and the lower limit tccq of the duration of the time interval from the leading edge of the clock pulse to the moment the output signal changes, as well as the preset and hold times tsetup and thold, which determine the time interval before and after the arrival of the clock pulse edge, during which the values ​​at the inputs should not change. tpcq is the propagation delay of the clock input - output Q path (until the new value is fully set) of the sequential logic. tccq is the response delay of the clock input - output Q path; -E

In this case, the command execution time means the number of clock cycles after which the next command can be launched for execution. If a command is executed in one cycle, then the command following it can be started already on the next cycle). Data load instructions are executed in one clock cycle if there are no conflicts, and in two clock cycles if the pipeline must be suspended to resolve the conflict, so their CPI = (0.6) (1) + (0.4) (2) = 1 ,4. Conditional branch instructions are executed in one clock cycle if the branch is predicted correctly, and in two clock cycles otherwise, so their CPI = (0.75) (1) + (0.25) (2) = 1.25. Unconditional branch commands have CPI always equal to two. ; -}