EE 477 Assignments
EE 477 Assignments
Please note assignments are in reverse order. The newest assignments are at the top.
A testing waveform for lab 3 has been posted. Use this for schematic and layout simulation
Solution to Assignment 6 has been posted.
Solution to Assignment 5 has been posted.
Assignment 5 has been posted.
Due 11/1/16
The solution to Assignment 4 has been posted.
The solution to Assignment 3 has been posted.
The solution to Assignment 2 has been posted. (Added later) Note that the solution to the second latch is incorrect. The /set and /reset signals could be exchanged but that gives set priority. So instead of exchanging the second latch set and reset signals we use set and reset active high in the second latch and convert the NAND gates to NOR gates. The output of the second latch is Q and the feedback to the second latch mux should be /Q. The problem called for set and reset to be active low but there is no obvious solution for the second latch that allows that while still making reset priority.
Assignment 4 has been posted.
Due 10/3/16 at 5 PM
A corrected solution to Assignment 1 has been posted.
Assignment 3 has been posted
Due 9/26/16 at 5 PM
The solution to Assignment 1 has been posted.
Assignment 2 has been posted.
Due 9/19/16 at 5 PM
Assignment 1 has been posted.
Due 9/12/16 at 5 PM
8/17/16 Please read Ch. 1 of the text (Kang, Leblebici and Kim)
through p. 27