EE477 - f16 hw6

Homework Assignment #6

E477 Fall 2016 Professor Parker

Hardcopies due in the course boxes in the basement of EEB 5 PM 11/14/16

OR Ecopies due 5 PM 11/14/16 using the "Assignment" Function on DEN

Assume lambda is .1 microns. Assume Vdd is 1.8 V, V_tp0 is -.7 V. and V_tn0 is .7 V. V_tpbodyeffect is -.9 V. and V_tnbodyeffect is .9 V.

Tox = 57 angstroms for thinox, and 5000 angstroms for thick oxide. Metal thickness is .5 microns.

You can use these values for transistor betas: _n (beta)= 219.4 W/L _ A(microamps)/V² and _p (beta)= 51 W/L _ A/V² .

_₀ (epsilon) = 8.85 X 10 ^-14 F/cm, __oxide(epsilon) = 3.9*_₀, and __silicon(epsilon) = 11.7*_₀.

N_A=4X10¹⁸cm^-3 (substrate doping)

N_D=2X10²⁰ cm^-3 (source/drain doping)

N_A(sw)=8X10¹⁹ cm^-3 (Sidewall (p+) doping)

n_i²= 2.1X10²⁰ cm^-3 (intrinsic carrier concentration of silicon)

x_j (diffusion depth) =32 nm

KT/q= .026 V (thermal voltage)

1) (20%) Compute the worst-case rising and falling RC time constants at the output of the circuit below using the Elmore delay method. Assume all transistors are unit sized and there is no wire resistance or capacitance. The circuit for the compound gate is also shown.

2) a) (10%) The output of the compound gate from Problem 1 is connected to seven 2-input NAND gates and an inverter through a long wire as shown in the figure below. Assume for INV and NAND gates that rise time is equal to fall time, where Rp=500Ω. Assume for the compound gate and NOR gate that rise time is equal to fall time, where Rn=400Ω. For each individual gate (INV, NAND, NOR, compound gate): Cgp=Cdp, Cgn=Cdn, Cgn=20fF. Rp and Rn are the channel resistance for a single NMOS and PMOS transistor. Assume the pi-model for the long wire (we only model the wire for the specified section in the figure). The wire resistance and capacitance are Rw=100Ω and Cw=400fF. Compute the rising RC time constant at node Z using lumped RC delay analysis. Re-compute the rising time constant using Elmore RC delay analysis.

2) b) (10%) Insert a pair of inverters at 1/3 and 2/3 of the way along the wire. For the inverters, assume that rise time is equal to fall time, so that Rn=Rp=500Ω, Cgp=4*Cgn; Cdp=Cgp, Cgn=Cdn, Cgn=20fF. Use the pi-model for the wire. The wire resistance and capacitance are Rw=100Ω and Cw=400fF. Compute the rising time constant at node Z using Elmore RC delay analysis. Compare this result with the one found in part (a) using the same method.

3) (10%) Assume a wire is 320 microns long and the width of the wire is 6 microns. Assume Rint = .1 ohms/square, and C = 50 ff/microns. Compute the actual wire delay using the distributed model.

4) (8%) Compute the gate-source side of the channel capacitance for an PMOS transistor in linear and saturation region. The PMOS transistor dimensions are: W=8 lambda, L= 3 lambda. Assume L_D=10 nm.

5) (8%) Use the fringing field figure on p. 274 of the text. Assume w/l = 0.4, and w/h = 0.1. Estimate the fringing field factor if t/h=0.4 and t/h = 1.

6) (8%) Assume electrons in a wire on a CMOS chip move at .00025 m/sec and the rise/fall time on the wire is 0.1ns. At what wire lengths are we forced to consider inductance?

7) (10%) A control signal driven by inverter A with unit size transistors fans out to drive 10,000 other inverters that are three times the size of inverter A. Assuming wire resistance and capacitance are negligible, design a superbuffer to drive this control signal. You can assume Cdn=Cdp=Cgn=Cgp=C for inverter A. Indicate the number of stages (without including the first unit size inverter A) and the device sizing for each stage.

8) (8%) Explain the meanings of setup time and hold time for a flip flop. How would the minimum clock period be affected if t_hold is greater than t_q+t_L2prop+t_comb? t_hold is the hold time, t_q is the clock-to-Q time, t_L2prop is the propagation delay in the feedback path of the second latch, and t_comb is the propagation delay of the feedback combinational logic.

9) (8%) Compute the Cdn for the source diffusion of a minimum size NMOS transistor with the smallest diffusion possible.