IRSIM Frequently Asked Questions

FAQ : Magic IRSIM HSPICE PowerView Verilog Cadence Misc

Q: IRSIM tells me that I have pending events. What does that mean and is that bad?

This means that at the time that the simulation step ended, not all of the nodes in your simulation have settled. You can find out which nodes have pending events with the printp command.

If your circuit is still working, then even if you have pending events it is ok. However, this might be an indication that if your increase your clock speed much more, your circuit will begin to operate incorrectly.

Q: When I bring up IRSIM, it says that I have shorted transistors. What does this mean?

This means that you have some transistors that have their source and drain shorted together. So unless you are trying to build a capacitor, this is not a good thing.

Q: When I bring up IRSIM, it says that I have parallel transistors. What does this mean?

This means that more than one transistor have the same gate,source, and drain terminals. If you've folded transistors (like maybe for a large driver), then you will have transistors in parallel. This is not a bad thing, provided that you meant to have parallel transistors.

When running simulations including the pad frame, some groups have been frightened by the extremely high number of parallel transistors that irsim reports. Keep in mind that the pad frame alone has very many parallel transistors (large drivers with folded transistors). The pad frame alone reports: parallel txtors: n-channel=748 p-channel=714

Q: When I try to do ext2sim, I get a whole slew of warnings and errors. What could be the matter?

It is possible that ext2sim cannot find the subcells of your layout. Remember that .ext files have hierarchy. There is a way to have ext2sim expand its search path beyond the current directory. See the ext2sim manual page.

Q: What are the ext2sim options that are enabled in the setup file? What do they do? Why do we use them?

The ext2sim options that are enabled are -c 1 and -R. The -c 1 option sets the capacitance threshold to 1fF. This means that any cap smaller than 1fF will be ignored. This makes sure that you are not on the margin for problems like charge sharing.

The -R sets the resistance threshold to infinity.

Make sure that you have these options enabled when you run ext2sim.

Ext2sim options are explained more fully in the ext2sim man page and the extcheck man page.

Q: I want to save the state of my simulation, so that I don't have to keep running my dorky setup command file every time. How can I do this?

There are 2 ways to save the state of a simulation in irsim. The first way saves the state of the sim as well as the history. The second way only saves the state.

The command dumph will dump the history of the simulation to a specified file. The readh command will read that history back out. Please take a look at the irsim manual page for specifics.

The > command will write only the state (not the history) of a simulation to a file. The < command will read this back out. This is especially useful for running very long tests, where the history buffer of irsim gets huge. You can break up your test and at the end of each piece, write the state to a file. When you start up the next piece, just read that state back in.

Q: How do I flush out the history buffer?

When you run very long simulations, you will find that the hsitory buffer gets unmanageably large. The command "flush" will empty the history buffer. So you can put this in your .cmd files periodically, if you don't want the history buffer to get too large.

Q: I have a vector nodes from a7 to a0. Is there easy way to define vector without typing all vector nodes?

vector A a{7:0} is equivalent to

vector A a7 a6 a5 a4 a3 a2 a1 a0