A final version of Assignment 5 solution has been posted. I think we had the wrong link before.
Assignment 5 solution has been posted. Note problem 9 is tricky - capacitance not FFF, and Problem 11 inductance not whether it is required. Problem 4 had a typo and has been fixed.
Lab 3 has been posted here and is due Dec. 9, 2021 at 4 PM.
Assignment 5 has been posted here and is due Nov. 22, 2021.
Lab 2 has been posted here and is due Nov. 15 at 5 PM
Lab 1b has been posted here and is due Oct. 29 at 5 PM.
Lab 1a has been posted here (as well as on D2L) and is due Oct. 22, 2021.
The solution to Assignment 4 has been posted.
Assignment 4 has been posted and is due Sept. 30 at 11:59 PM.
The solution to Assignment 3 has been posted.
The solution to Assignment 2 has been posted. Note in problem 7a, a tighter (and better) range would be if out <= 1.6 v, if we assume there is no way for out to be set higher than 1.6v. The only way for out to be set higher than 1.6v would be if the input somehow had been higher prevously.
Assignment 3 has been posted and is due Sept. 21 at 11:59 PM.
The solution to Assignment 1 has been posted.
Assignment 2 has been posted and is due Sept. 14 at 11:59 PM.
Assignment 1 has been posted and is due Sept. 7 at 11:59 PM.
Please read the attached Foreward to a draft text on VLSI for class 8/24/21
Please read Ch. 1 of the text (Kang, Leblebici and Kim 4th edition)
through p. 27 for class 8/24/21