Homework Assignment #4

EE477, Fall 2016

Assume for the problems below that V_dd = 1.8 V, V_tp0 is -.7 V. and V_tn0 is .7 V. V_tpbodyeffect is -.9 V. and V_tnbodyeffect is .9 V.

Assume ß_n (k_n)= 219.4 W/L µ A(microamps)/V² and ß_p (k_p)= 51 W/L µ A/V²

lambda = 100nm

Problem 1. An inverter is in segment D of the input/output voltage transfer curve, and Kn=Kp.

a. (2pts) In what regions of operation are the transistors?

b. (10pts) What range of input values will prevent it from moving into other segments after reaching steady state?

Problem 2. For an input of 0.8V, an inverter outputs a value of 1.55V. Assume that Kn=Kp.

a. (5pts) In what regions of operation are the transistors?

b. (2pts) What segment of the input/output voltage transfer curve is the inverter in?

c. (10pts) What range of output values would allow the inverter to stay in the segment found in Part (b)?

d. (10pts) What is the current that flows through the transistors?

Problem 3. The sizes of the PMOS transistor and the NMOS transistor of an inverter are both minimum size.

a. (10pts) Describe how the input/output voltage transfer curve appears. For what input value does segment C of the transfer curve occur?

b. (4pts) Which transistor stays on for more of the input values?

Problem 4. While measuring the input/output voltage characteristics of an inverter, a current spike was found to occur when V_in=0.95V.

a. (5pts) What is the ratio of Kp to Kn?

b. (5pts) What is the relationship between PMOS and NMOS transistor widths and lengths?

c. (5pts) What is the current that flows through the NMOS transistor if it is sized to have minimum length?

Problem 5. (6pts) An inverter has been designed with Kp/Kn=1.6. When the inverter is in segment C of the voltage transfer curve, what is the input voltage

Problem 6. The input signal and corresponding output signal for an inverter are shown below.

a. (3pts) What is the rise time of the output?

b. (3pts) What is the fall time of the output?

c. (3pts) What is the rising delay?

d. (3pts) What is the falling delay?

PLEASE DO PROBLEMS 7-9 AFTER LECTURE ON TUESDAY

7. (5pts) Define VIH, VIL VOH, and VOL and write down the definitions of HIGH noise margin and LOW noise margin.

8. (5pts) If we want to design an inverter with high noise immunity, would we want a large range or a small range of V_OL to V_OH values compared to the range of V_IL to V_OH values? Briefly explain your answers.

9. (4pts) What does it mean to have a noise margin NMH of 0.4 in terms of the amount of noise that can be added to the signal and still have correct results?