Homework Assignment #1

EE 477, Fall 2016, Professor Parker

Hardcopies due in the course boxes in the basement of EEB at 5:00PM 9/12/16

OR Ecopies due at 5:00PM 9/12/16 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.


  1. A combinational circuit is created to convert a positive binary number into its negative 2's complement form. The input is a binary number given by a3a2a1a0, where a3 is the sign bit and a2a1a0 is the value. Assume that a3 is always 0 since the inputs are positive. The output is b2b1b0 where b3 is the sign bit.
    1. Show a truth table for the 2's complement converter.
    2. Give the Boolean expressions for the outputs (b3, b2, b1, b0) in terms of the inputs (a3, a2, a1, a0).
    3. Draw the circuit diagram of the 2's complement converter at the gate level using only INV, NAND, and NOR gates.


2. Show the gate level implementation of the following function using only INV, NAND, and NOR gates.

Out = [A + B(CD + EF) + GH](I + J)K

3. Out = /{ABCD + E(/F) + G[H(/I) + (/J)K + (/L)(/M)(NO + P)]}

    1. Show the gate level implementation of the function using only INV and NAND gates.
    2. Show a compound gate transistor level-diagram of the function given in Problem 3a. Do not manipulate the function.
    3. Compare the implementations in Problem 3a and Problem 3b in terms of number of transistors. How many transistors does each require?


4. Show a compound gate implementation of the function below at the transistor level:

out = W(A XOR B) + (A XNOR B)(XY + Z)

You may need to manipulate the equation to get in complement form. Do not use additional inverters at the output of the compound gate. Assume that complements of the inputs are available.


5. Show the transistor-level CMOS circuit and the stick diagram of a 6-input NAND gate. Label the layers using different colors for the different layers as shown in lecture, and indicate the names of the materials. Also label the inputs/output and the source/drain of each transistor.


6. F = A XOR (B XOR C)

    1. Design the function above using logics. You may only use INV, NAND, and NOR gates. Show the transistor-level CMOS circuit for this design.
    2. Design the function above using transmission gates and show the transistor-level CMOS circuit.


7. Show a design at the transistor level of a 7-input MUX built using transmission gates. How many transistors are needed? How many transistors are needed for a general n-input MUX?


8. Design a latch that has one possible data input (D) plus the feedback path (Q). The latch should load in data when the clock is low. The latch can be synchronously set and reset when the clock is low. When Set=1, the output of the latch that is fed back to the latch's MUX is high (Q=1). When Reset=1, the output is low (Q=0). Set and Reset functionalities can only take effect when an enable signal is high (Enable=1). The Reset function should have priority over Set. This means that when both Set=1 and Reset=1, Reset will have priority and the output will go low (Q=0).

    1. Draw both the gate level and transistor level implementations of this latch.
    2. Using the waveform below, sketch the outputs Q and Q_bar.