EE477 - f16 hw3

Homework Assignment #3

EE 477 Fall 2016 Professor Parker

Hardcopies due in the course boxes in the basement of EEB 5 PM 9/26/16

OR Ecopies due 5 PM 9/26/16 using the "Assignment" Function on DEN
To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work. Turn in EITHER a hard copy or ecopy, not both.

Assume for the problems below that V_dd = 1.8 V, V_tp0 is -.7 V. and V_tn0 is .7 V. V_tpbodyeffect is -.9 V. and V_tnbodyeffect is .9 V.

Assume ß_n (k_n)= 219.4 W/L µ A(microamps)/V² and ß_p (k_p)= 51 W/L µ A/V²

lambda = 100nm

1. (10%) A PMOS transistor is in the saturation region. What values of the drain voltage keep it in the saturation region if Vg = .1v, and Vs = Vdd?

2. (10 %) An NMOS transistor has Vs = 0.7 V. V_d = 1.7 V. Is the transistor in the saturation region of operation when Vgs =1.3 V?

3. (5%) Show a cross section and identify the parasitic transistors that cause latch up for a p-well process. How does a silicon-on-insulator process prevent latchup?

4. (5%) Assume the channel between drain and source of a PMOS transistor is formed so that the transistor is in linear region. Is the channel formed with electrons or holes? If we continuously hold Vgs voltage constant while decreasing Vds, what would happen to the channel underneath the gate area? Would the transistor be at t=infinity in linear, saturation, or cut off region?

5. (7%) A design rule that specifies minimum width of metal prevents what type of fault? Minimum metal spacing prevents what type of fault?

6. (10%) Shown below are IV curves for NMOS transistors. Sketch similar curves for PMOS transistors.

You will probably want to wait until after Tuesday's lecture to work the remainder of these problems 7-10 below.

7. a) (5%) A PMOS transistor is used as a switch to transfer a voltage. If Vgp = .3v, and Vin = 1.6v, with Vout = 0.0v at t=0+, where is the transistor source (at the output or at the input) and is there body effect?

b) (5%) What is the region of operation of the PMOS transistor at t = infinity?

c) (10%) Assume the transistor width is minimum size and the length is three times minimum size. Compute the drain current flow I_DSP^{at t = 0+ and at t=infinity.}

8. a) (7 %) Identify the sources and drains in a transmission gate at t=infinity when Vin = .3 V and Vout = 1.1 V at t=0+. Vgn = 1.4 V, and Vgp = .5 V.

b) (8 %) What regions are the two transistors in when t approaches infinity? Be sure to justify your answers.

9. (15%) In the circuit below, what are the voltages at node A and Out at t=infinity? Assume Vin = Vdd, VA = .9v, and Vout = 0.1v, all at t=0+.

10. (5%) What is the effective channel resistance of an NMOS transistor of 1.6 microns width and 4 lambda length? Assume Vgs=1.7 V, Vds= .5V, Vg=Vdd.