Homework Assignment #2

EE 477, Fall 2016, Professor Parker

1. Flip flop Design: (25)

Review the lecture notes on 9-1-F16 where Prof. Parker designs a flip flop with asynchronous reset capability.

a. Modify the design to support both asynchronous set and reset of the output while being positive edge triggered. Consider both /set and /reset signals to be active low. Whenever any of the /set and /reset would be asserted, the output will be set to VDD or cleared to 0 regardless of the clock and data signals, respectively. Assume the /reset signal has a higher priority to /set meaning if both /set and /reset are asserted the output will be reset. If both the /set and /reset signals are inactive the data on the D input will be captured by the flip flop on the RISING edge of the clock. (10)

b. Modify your design in Part a so the /set and /reset will be synchronous to clock signal. In this case, /set and /reset signals can only affect the output on the rising edges of the clock. (10)

c. Modify your design in Part a so the flip flop will be negative edge triggered rather than being positive edge triggered. In this case, the data on the D input will be captured by the flip flop on the FALLING edges of clock if the /set and /reset signals are inactive. (5)

You do not need to draw what is inside of each gate. Show us an implementation using transmission gates for the multiplexers and clearly label the inputs to each transistor.

2. Logic Design using Transmission Gates: (20)

Design the following functions using transmission gates. Assume that both the inputs and their complements are available.

a. F1 = (A XOR B).C

b. F2 = AB + C

When designing your logic using transmission gates make sure 2 conditions are met:

1. Always there is a path from primary inputs to the output (i.e., the output will not be float when any input is applied to the circuit).

2. The output is not simultaneously driven by multiple paths from the primary inputs resulting in contention.

Hint: You can expand the function of interest initially with respect to a variable like A as F1=A.G1+~A.G2 and then expand both G1 and G2 with respect to B (or another variable) until you reach a primary input like: (~C, C, 0, 1).

3. CMOS Fabrication Process (40):

a. Sketch the steps involved in patterning metal1 using a negative photo resistance. (5)

b. Enumerate lithographic steps required for creating an NMOS transistor. Sketch the cross view of an NMOS transistor labeling every layer based on the lithographic steps you enumerated. (10)

c. Explain the purpose of n-taps and p-taps in the physical layout. What voltages do we tie the n-tap and p-tap to in the CMOS process? (10)

d. Why do we use thin oxide instead of thick oxide under the gate region of the transistor? (5)

e. What is the importance of depositing poly before diffusion when fabricating transistors? (5)

f. Show a case where a parasitic MOS transistor can form in a layout. (5)

4. Basic Layout: (15)

Draw the cross section view for the figure below along the vertical yellow line. Please use the legend to find the information associated with each layer.