University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #3 (worth 20% of final grade) - Minor Revision

Module Design, Cadence and SPECTRE

Due 12/6/16 7:00 PM

There will be no extensions so plan your time accordingly!

Required contents of the report appear in purple.

This is a long lab so be sure you scroll to the end to see all the information.

Rules:

You can use any combination of multiple clocks you wish, but only clock is an input to the circuit and you will have to design circuits to generate the other clocks.
You need to generate all inverted inputs, including /clock and /load They are not inputs to the circuit You need to generate them if you need them.
You must use the cells you designed in labs 1 and 2 to build your neuron and your neural network. Do not change the circuit structure of your cells unless your cells do not meet the requirements of lab 1 or 2 (i.e. you lost points). You can rearrange the layout slightly or resize transistors as needed while still meeting the requirements of lab 1 and 2. Do not change the methodology by rotating transistors, rearranging transistors, connecting inside the cell on different layers, or changing your interconnection strategy (for example, you might decide that all inputs come in the top of the cell, so you can't change that). You can move ntaps and ptaps around.
You must have ntaps and ptaps according to the rules. Make sure your ohmic contacts (ntaps and ptaps) meet the following requirement: Every cell should have a well and substrate contact, including transmission gates, and of course the taps should be connected to Vdd and Gnd. For larger cells, include at least two contacts per 50x50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact. For all your contacts, you will get the best performance if you use multiple minimum-size contacts for large contact areas and not large contacts, as Cadence will do for you automatically.
You can tune the circuits by changing transistor sizes as needed or to squeeze out empty space while still meeting the requirements of lab 1 and 2. You can modify the layout of your cells from Labs 1 and 2 in minor ways in Lab 3 if you can see some ways to make the circuits smaller or faster. You can rotate and flip cells about the x and y axes.
You cannot remove unused inputs or unused logic from your cells.
You can use metal layers 1-4 for the neuron, and layers 1-6 for any external connections that go to the inputs/outputs of the neuron.
All signals should use the names we have given below.
As in Lab 2, the output transition of the flip flops including any setup time at any following flip flop inputs should occur before the next rising edge of the clock.
For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected.
On your final neuron layout, all inputs and outputs to the circuit must be routed to the edges of the layout and must be labeled using the pin names.

12. Include a title page in your report that includes your name, student number, email address and date. Your report file name should be Lastnameusernamelab3.pdf. Do not submit other file formats, like .doc or .txt.

On the cover page of your report, please give the final area and delay of your final neuron design, and your final area*delay product. The delay you should measure with SPECTRE simulations of your layout for your final result is the clock cycle or clock period of the neuron layout assuming correct operation. Your output should appear before the next rising edge of the clock. The faster your clock cycle, the faster your circuit will function. Measure the area of your design in square microns. Your area should be the bounding box area of your design. If your design is not rectangular, include the wasted (empty) area in your area calculation. Compute the area-delay product of your design and report it clearly at the beginning of the report so we can find it. Compute an area-delay product that is the area in square microns times the clock period. If you compute the area-delay product wrong, or you do not compute it you will lose points.

The Digital Neuron

This lab is the design of a special-purpose digital circuit that mimics a neuron (brain cell). Be sure to finish and test your schematic of the neuron before you start the neuron layout.

There are 5 inputs to the neuron:

a single-bit data input to the neuron, D that could be different every clock cycle
a single-bit inhibitory input I,
Load control signal, that allows the output firing ff to be loaded with a new value,
Reset control signal that resets all the flip flops by loading 0.0v,
and a clock with 50% duty cycle.

Name your signals as shown in bold above. The output should be named AP. It is important you follow this naming convention so we can verify that your circuit works.

The basic Neuron Function:

Each data input and control input has a single bit.
The inhibitory input I is a single bit. It prevents the neuron from firing as long as it is held to "1" (Vdd)
The neuron output contains one firing flip-flop you designed in Lab 2, and the output of the flip-flop AP represents the output of the neuron.
The neuron "fires" when the input D is a sequence 1 0 1, and I =0. So the neuron remembers inputs using additional flip flops until the proper pattern is detected and then the neuron sets the output flipflop for one clock cycle and resets all additional flipflops.
After the negative edge of the clock, if the neuron fires, the output of the firing flip-flop AP goes from low to high. The output remains high until the next falling clock, when it is lowered.
Load is normally held high, but is lowered if we want to emulate a neuron failing to fire due to lack of sleep or similar circumstance.
Note that you might find a way to use the compound gate you designed in Lab 1, and you might need more than one of these gates. You do not have to use it at all.

For example, if the inputs is 101 in sequence, the output flipflop will be set (fire) and all memory of accumulated inputs will be erased. Then, if the sequence of 3 D inputs is 101 again, the neuron will fire again.

Design the circuit to be a Mealy Machine, where the output (the firing flip flop) is derived from the present state (all other stored values) and the inputs during the current clock cycle. The next state (all other stored values) are also a function of the present state and the inputs. The firing flipflop does not affect whether the flip flop fires again in subsequent clock cycles.

Design variations for the Input memory and logic: You have the option to store individual inputs separately as they arrive, and test them together to see if they have a 1 0 1 pattern before firing the neuron. Or you can change the state as inputs arrive, possibly saving storage or computation space. In the first case you need to be able to store a count of at least 2 for each D input, and in the second case you need to be able to store the state information, which might be 2 as well. Feel free to try other variations of these.

A block diagram of the neuron is shown below.

Sample Timing Diagram for the Neuron:

Below is a sample timing diagram for the neuron. On the first falling edge D is 1, and stays 1 for another falling edge, then goes to zero for a falling edge, then back to 1 thus the output AP fires.

The Laboratory Steps:

1. Design your neuron circuit and create a Cadence circuit (schematic) diagram using the circuits/cells you have designed in Labs 1 and 2. You cannot design new cells for Lab 3. Include your logic/gate level diagram for your neuron.

2. Simulate your neuron schematic to ensure that your design works correctly. Use the following sequence of inputs for initial testing of your schematic:

a) Set load to 1 and keep it high. All other inputs except clock (and reset data if you use it) should be 0, including I. Reset your neuron flip flop.

b) Set load to 1 and keep it high, while keeping I = 0. Then test your neuron by sequencing through D=0 to D=1 to D = 1 to D = 0 to D = 1 to D = 0. (2 different values).

c) Now set I = 1 (inhibition), leave load =1 and sequence through the same inputs. The output AP should be low.

d) Reset the neuron flip flop. Now set load to 0 (zero). Set the data input D to 1, and I = 0, then on the next clocks 0 then 1 with I = 0. The flipflop output should remain zero.

3. Lay out your neuron.

4. Use LVS to verify your layout prior to SPECTRE simulation. Important note: Any pins in your layout labeled the same should be physically connected to each other.

5. Simulate your neuron layout with SPECTRE to ensure that your design works correctly using the same sequence of inputs as in Step 2, and measure the smallest clock period for the neuron. Show the waveforms you used to measure the clock period.

a. Show all inputs D, reset, load and I together in a panel and in a second panel show the output AP and clock together. (note: not following instructions will lead to deduction of points).

b. Submit a zoom-in of the same waveform around the time the output transition occurs.

Note: Be sure the output transition occurs before the next rising edge of the clock. The output transition should reach at least 90% of Vdd before the rising edge of the clock.

Testing Strategy:

Here is a testing strategy that might be useful to you: Design the schematic first block by block and test. Then design the layout and test each part as you build it.

Design and test at each stage. Design the output flip-flop first. Then design the other storage, logic and the output of the logic that makes the neuron fire if the logic creates a "fire" situation. Test the logic separately first. Then add the flip-flops. Then test the entire neuron.

Final Report:

Include in this lab report, in order:

A cover page showing name, student number, email address, date, and AREA-DELAY product. The delay you should measure with SPECTRE simulations of your layout for your final result is the clock cycle or clock period of the neuron layout assuming correct operation. Your output should appear before the clock rises again. The faster your clock cycle, the faster your circuit will function. Measure the area of your design in square microns. Your area should be the bounding box area of your design. If your design is not rectangular, include the wasted area in your area calculation. Compute the area-delay product of your design and report it clearly at the beginning of the report so we can find it. Compute an area-delay product that is the area in square microns times the clock period. If you compute the area-delay product wrong, or you do not compute it you will lose points.
A description of the neuron you built, including a transistor-level and gate-level circuit diagram (schematic) printed from Cadence, your simulation results (including waveform images) and a description of how your circuit was constructed using existing cells.
A floorplan of the neuron layout. A floorplan shows where on the layout you placed functions, without showing the details of the functions. Cadence might have a tool to do this for you but you need to draw it yourself for clarity. Try this link to see an example. You do not have to draw your floorplan over your layout image but it helps clarity.
Your neuron layout image and neuron layout simulation results as images. Make sure the layout and simulation images are of high enough resolution so that we can zoom in to check things. Put your input and output waveforms onto multiple graphs so we can read them more easily
A description of the simulation experiments you ran with SPECTRE for the neuron.

Include (not in the report but as separate files)

1. SPECTRE netlist files for both schematic and layout of the neuron, generated by Cadence, which will include the technology file, the graphical stimulus files and the circuitry netlist. We need everything you used so that we can run your simulations in case your results are unexpected.

2. High resolution images of your neuron layout and waveform files. This is so we can view the layout properly to check details. Make the waveform signals thick enough for us to see them.

Tar this report along with the files specified above. Other formats besides Tar will not be accepted. Upload your report to the assignments function of Blackboard, including your layout and simulation files as a TAR file so that we can test (simulate) your circuit to be sure it performs as specified. Include SPECTRE netlist files for final schematic and layout of the neuron, generated by Cadence, which will include the technology file, the graphical stimulus files and the circuitry netlist. We need everything you used so that we can run your simulations in case your results are unexpected.

IMPORTANT: Once you upload there will be no deletions or reuploads allowed. All files should be in a single Tar file, uploaded to DEN. Files uploaded to the dropbox will not be graded. All layouts must be in color unless you obtain prior permission. Failure to follow these instructions could result in deduction of points.

Discussion

For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product. Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. Pay close attention to the specific delay you are to measure.

End of Lab 3