Lab 8
EE 421L
Authored by:
Johnathan Widney - widney@unlv.nevada.edu
Benjamin Molina - molinb1@unlv.nevada.edu
Matthew Lord - lordm1@unlv.nevada.edu
5 December, 2023
Prelab
Going through Tutorial 6 on Dr. Baker's website. Note, half of Tutorial 6 was covered previously in homework assignment #5 in EE 421 class. This lab will cover the second half of that tutorial.
For reference, we will be continuing the tutorial from this step, the extracted view of the padframe.
< Schematic view of a single pad
Symbol view for a single pad >
< Schematic view for the padframe
Symbol view for the padframe >
Schematic view of the chip
Layout view of the chip with the above components
The rest of the tutorial requires extracting, DRC-ing, and LVS-ing the layout, however, as of Dec 1 of this year, UNLV's licenses for Cadence expired, and thus we are not able to verify, DRC, extract, or LVS any layouts. This will conclude the prelab portion.
Lab Work
Below will detail the schematic and layout of the individual components we will use in the chip. At the end, we will show the schematic and layout of the completed chip.
Schematic and layout of Ring oscillator
Schematic and layout of inverter
Schematic and layout of NMOS transistor
Schematic and layout of PMOS transistor
Schematic and layout of 2-input NAND gate
Schematic and layout of 2-input NOR gate
Schematic and layout of 25k resistor
Schematic and layout of a Voltage divider (25k and 10k)
Schematic and layout of a charge pump
Schematic view of our chip (similar to the tutorial, but with additional components, as shown)
Additional components: 2-input NOR gate, and a charge pump.
Layout view of the chip
This is a diagram of the chip's pins, below are the connections we have for each pin. Note, pins that have no connection will be marked "NoConn":
Ring Oscillator Output
Ring Oscillator VDD (in)
NoConn
Voltage Divider Output
Voltage Divider Input
NoConn
NMOS Drain
NMOS Gate
NMOS Source
NoConn
PMOS Source
PMOS Gate
PMOS Drain
PMOS Body (Bulk)
Inverter Input
Inverter Output
Inverter VDD (in)
NoConn
NAND VDD (in)
gnd! (Ground)
NAND Input (B)
NAND Input (A)
NAND Output
NOR VDD (in)
NOR Input (A)
NoConn
NOR Input (B)
NOR Output
Charge Pump VDD (in)
Charge Pump Input
NoConn
Charge Pump Output
NoConn
NoConn
NoConn
25k Ohm Resistor Input (L)
NoConn
25k Ohm Resistor Output (R)
NoConn
vdd!
Instruction of operation:
Disclaimer:
The chip must be grounded, this connection will be pin 20. Failure to connect the gnd! and various VDD pins (either no connection or connected to an incorrect source) will result in the chip malfunctioning and operation results are not guaranteed. The chip could become damaged as a result of these pins not being properly connected.
Also as a general rule, inputs and outputs should not be mixed.
Zip files and backup
Backups were performed by creating a Google folder and uploading screenshots and files to the folder seen to the left.
Downloadable zip file here: