Lab 4
Prelab
Previous lab work is backed up via this website, Google Cloud, and locally on multiple devices.
Tutorial 2 walkthrough:
Schematic view of NMOS transistor
Symbol view of NMOS
Parametric analysis of the NMOS transistor
Initial layout view of NMOS, successful DRC, but failed LVS
Improved layout design, again successful DRC, but failed LVS. Need to improve schematic/symbol to account for missing pins.
LVS Fail
Library of current 3-pin NMOS schematics, symbols, layouts, and extracted views.
Adjusted schematic design to include 4 pins, to tie one to ground to then allow layout and extracted versions to successfully pass LVS.
Detailed list of LVS pass, netlists now match.
LVS pass with netlists matching.
Uploaded extracted view and simulated it parametrically, highlighted netlist detail to show that this is utilizing the extracted layout.
Repeating steps but for a PMOS configuration, doing this in a more expedited manner since eliminating minor mistakes from making the NMOS design.
PMOS schematic
PMOS symbol view
PMOS layout view with DRC successful pass.
PMOS extracted view.
Moving on to simulation of our PMOS design.
Schematic view of the circuit we will simulate.
Parametric analysis of the base schematic design before using the extracted layout.
Parametric analysis using the extracted layout. Highlighted in the netlist to show that this is using the extracted values from the layout.
Lab Report
ID vs. VDS/VGS/VSD/VSG (NMOS/PMOS)
NMOS ID vs. VDS schematic. Note, dimensions are 6um / 0.6um (600nm) Length/Width.
Parametric analysis. Note, VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps.
NMOS ID vs. VGS schematic. Note, dimensions are 6um / 0.6um (600nm) Length/Width.
Parametric analysis. Note, VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps.
PMOS ID vs. VSD schematic. Note, dimensions are 12um / 0.6um (600nm) Length/Width.
Parametric analysis. Note, VSG varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps.
Notice the distinction between VGS / VSG, and VDS / VSD. VGS and VDS are associated with NMOS, while VSG and VSD are associated with PMOS for purposes of this analysis.
PMOS ID vs. VSG schematic. Note, dimensions are 12um / 0.6um (600nm) Length/Width.
Parametric analysis. Note, VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps.
6u/0.6u NMOS device
Layout of a 6u/0.6u NMOS device with 4 MOSFET terminals connected to probe pads:
Layout of a singular probe pad
Cadence Filepath Error
Had difficulties downloading the zip file containing the lad layout and other components. Cadence wouldn't update it's file directory to upload the file. Was continually loading and upload was stuck at 0%. Don't have the knowledge to recreate a pad component from scratch. I have the technical know-how to complete the lab, provided I knew how to make a probe pad layout from scratch. Encountering this unexpected error has lengthened progress on the lab and halted it for a short time.
Cadence unable to upload the zip file for the components. The file directory sidebar also displayed a continual loading wheel on the mouse cursor (not shown). Troubleshooting steps included logging out and logging back in, changing directories, attempted using different flags when logging in, cancelled upload and re-attempted, finally closing out everything and restarting everything worked.
Schematic and symbol views for the probe pad.
Schematic view of the NMOS circuit to be simulated.
Layout view of the NMOS device. DRC pass
Extracted view. LVS pass
Zoomed in on layout of NMOS
12u/0.6u PMOS device
Layout of a 12u/0.6u PMOS device with 4 MOSFET terminals connected to probe pads. Repeating a similar process as above.
Schematic view of the PMOS circuit.
Layout view, with DRC pass.
Extracted view with LVS pass.
Zoomed in on layout of PMOS