Lab 2
Prelab
Downloaded, uploaded, and defined the zipped library of lab2.
Simulation result (of preloaded library)
Explanation of ADC and DAC
The ADC is the input voltage and has a minimum threshold determined by the Least Significant Bit (LSB), this LSB is required to be properly read by the DAC to output the encoding, i.e. output voltage. In other words, The ADC is an input of bits (digital) that increment in steps and these inputs go into the DAC (Digital to Analog Converter) which uses those inputs to produce a fluid analog waveform.
Calculating Least Significant Bit (LSB)
Calculating the LSB is provided by the following equation:
LSB = Vdd / 2^n (Where n is the number of bits)
For this lab, what is given is:
Vdd = 5V n = 10
Therefore, LSB = 5 / 2^10 = 4.88mV
Lab Work
Created a layout of a roughly 10k Ohm resistor.
Schematic view of a 1-bit DAC, note the two 10k resistors in series to create a 20k resistor.
Symbol view of the previous schematic.
Using the above symbol, created my own 10-bit DAC converter (left is the full view, the below is a zoomed view to show details. Note that the lowest symbol has a 10k resistor attached to it and gnd node.
Made a symbol view for my ideal 10-bit DAC. Made it in the same footprint as the one provided by Dr. Baker.
Determining Resistance
Because the resistors are set in a 2 resistor pair in series, and are also set in parallel with another resistor pair in series, simple voltage division reduces the resistance to 1 resistor. This effect cascades from B0 through B9, resulting in the final resistance of the 10-bit DAC being 10k Ohms.
Below is a visual representation of one bit:
The effect shown in a cascading view. (Click to expand/collapse)
The final output resistance is 10k Ohms
Calculating Delay
Delay for the circuit can be calculated with the following formula:
t_d = 0.7(R)(C)
Given the capacitive load of 10pF, the delay can be estimated as follows:
t_d = 0.7(10k)(10p) = 70ns
The schematic of my 10-bit DAC to test for delay.
Waveform result, when Vout reaches it's halfway point (1.25 V) it's roughly 70ns as calculated.
Schematic view of ADC to DAC with no load. Note: had to adjust VDD value to 4.9 V, was getting errors of blowup values for I, not sure how to correct.
Simulation result.
ADC to DAC schematic with 10k ohm resistive load. Since the internal resistance of the DAC I made earlier has a resistance of 10k Ohms, this should divide the output in half, given the other 10k load being in parallel.
Simulation result, we can see the output is indeed reduced by half due to the parallel resistors.
ADC to DAC schematic view with a 10pF capacitive load. There will be a roughly 70ns delay as calculated earlier.
Simulation result. Note the capacitor has smoothed out the output for Vout, instead of being in steps, it is one continuous line. This is expected.
ADC to DAC schematic view with RC load of 10k Ohms and 10pF. This is combining the previous two loads and the results should reflect both effects.
Simulation result. As expected, the result combines the delay and continuous line of the capacitor, and halves the input vlotage due to the resistor load.