Lab 7
Prelab
Going through the steps outlined in Tutorial 5 on CMOSedu website.
First we begin with making a ring oscillator using 31 connected inverter gates.
Here is a zoomed in section for better view.
Simulation results when running the schematic. Note is stays steady at 2.5 V, but only for a certain amount of time, then it begins to oscillate.
Simulation result after setting an initial condition.
A more concise version of the schematic using wide wires (busses).
Layout view of an oscillator, with a clean DRC pass.
Extracting and running an LVS results in a failed LVS, this is due to the current setup of the schematic, there are mis-matched pins.
Corrected schematic with proper pins that match the layout.
Rerunning the LVS results in a clean pass as the netlists now match.
Created a quick symbol for the oscillator and schematic to simulate it. We will also be testing the extracted layout values.
Simulation result with preset values and conditions as done earlier in this lab.
Simulation using extracted layout.
Lab Work
4-bit inverter schematic.
Symbol view for the above schematic.
Schematic used to test in simulation.
Simulation results. Note that capacitance alters the rise and fall time of the waveforms as well as the delay.
8-bit Logic gates
NAND Gate schematic and symbol. The CMOS schematic for this can be viewed in Lab 6.
NOR Gate schematic and symbol (since this is a new gate that hasn't been shown or made in previous labs, I've also provided the CMOS schematic for a single 2-input NOR Gate I created for this.)
AND Gate schematic and symbol. (And CMOS schematic I created for it since it's a new gate.)
Inverter Gate schematic and symbol (this was created in Lab 5, CMOS schematic can be viewed there.)
OR Gate schematic and symbol. (With my created CMOS schematic since this is a new gate.)
Simulation schematic to test all the gates.
Simulation results.
MUX / DEMUX
MUX schematic and symbol.
Simulation schematic to get a base understanding of how the MUX operates.
Simulation results to understand MUX operation.
8-bit MUX with one input for select.
Symbol for the above schematic.
Simulation schematic to test the 8-bit MUX.
Simulation results.
Recongfigured simulation schematic to test for DEMUX capabilities.
Simulation results.
Full Adder
Full adder schematic purely with MOSFETS. (CMOS schematic)
Symbol view (built previously from Lab 6)
Symbol / schematic for 8-bit Full Adder
Simulation schematic for 8-bit Full Adder to test functionality.
Simulation results.
Layout view for a single Full Adder (to show detail) includes clean DRC.
Layout view for 8-bit Full Adder with clean DRC pass
Extracted the layout and yielded clean LVS pass.
LVS net-lists matching.