Lab 3
Prelab
R_div layout view
LVS output results of netlists matching and DRC with 0 errors of the R_div.
Lab Report
10k n-well resistor layout view with 0 DRC errors.
Within the editor you can adjust the L and W, by clicking on the resistor sheet, and pressing "Q", you can manually adjust the L and W of the resistor in the menu window.
An explanation of how Length and Width play into the resistivity of a layout. Width for most resistors is typically 3.6um (microns) therefore Length is usually the adjusted value. If we know the desired Resistance (10k ohms) we can work backwards to find the necessary length and width. (in the layout above, we chose a width of 4.5 microns)
DAC layout, two resistors in series connected by one resistor in parallel to create voltage dividers.
Width and length of a resistor can be measured in the layout view of Cadence by using the ruler function. The keybind for this is "k".
DRC Pass
Majority of errors seemed to come from the n-well resistor layout. The odd thing was this same layout was used in a Tutorial and had no DRC errors.
LVS Pass
Due to DRC failure, was unable to produce an LVS pass.