Final Project - Lab

EE 421L

Authored by Johnathan Widney - widney@unlv.nevada.edu

21 November, 2023

Hand Calculations, Schematics and Design Discussion (first part of project)

Layout and Design (second part of project)

Hand Calculations, Schematics and Design Discussion (first part of project)

The architecture I chose for a non-inverting buffer was a charge pump. I will detail the dimensions and other design details in this section.

Basic design from the book of a charge pump. Included is a rough sketch of my own design and an explanation of strong inversion, which is how I am creating the capacitors for the chip. The sketch includes all the sizes which are calculated/explained below.

Hand calculations The capacitor at node A I arbitrarily chose as 100f F. With this, I calculated the right capacitor of node B to need a L=W= 63.25u which will have a capacitance of 10p F, this should allow an output voltage of greater than 8V. I chose to overshoot for 8V since the goal was to allow voltages greater than 7V.

Hand calculations of the capacitors for the input capacitance (inverters) and calculating delay. I calculated the input capacitance to be 81f F which yielded a delay of 2.2ns and a resistance of 1k Ohms, the resulting sizes for this input inverter were 24u/12u for PMOS/NMOS respectively. The remaining inverters I chose the sizes to be the common 12u/6u PMOS/NMOS inverters we've used all semester, and their input capacitance falls well beneath the required parameters.

CMOS schematic view of a charge pump. As calculated before, the input inverter has sizes of 24u/12u PMOS/NMOS. All other inverter PMOS/NMOS pairs have lengths of 12u/6u respectively. The NMOS' at the top have a L/W of 12u/600n. I chose these sizes as these are what we've commonly used for nearly all previous labs and in homeworks. For the capacitors, as calculated before, I chose 100f F for the left one, and 10p F for the right one and used NMOS' in strong inversion instead of a traditional capacitor. The corresponding length/width of each NMOS Cap is 6.3u/6.3u for the left cap, and 63.3u/63.3u for the right. These values slightly vary from my calculations as the AMI_0.6 rules auto adjusted these values.

Here is the symbol I created for the charge pump (buffer)

Here is a simulation circuit made to test various loads for the charge pump.

I went with a parametric analysis for the capacitor and had the source vary from 1 to 3 V for the input. Here are the simulation parameters. The capacitance will increase in steps of 200f F ranging from 0 F to 1p F.

Here are the simulation results. The outputs peak at a max of 8.13 V (no load) and the lowest peak with 1p F load is 7.38 V.

Voltage sweep simulation schematic

Voltage sweep simulation results.

Layout and Design (second part of project)

This section will detail the layout of the charge pump schematic, this consists of NMOS, inverters, and MOS Caps, all of which have been built in previous labs apart from the MOS cap. The details of sizes can be referenced previously in this lab.

The above layout yields a clean DRC pass.

The extracted view of the previous layout.

Ran an LVS, net lists match successfully.

Zip files and backup

As always, project was documented with screenshots that were stored locally on a machine, and in the cloud via Google Drive. The files for the project were downloaded and uploaded into the Google Drive folder seen here on the left.

Page updated

Report abuse