Lab 6
Prelab
Completing Tutorial 4 on Dr. Baker's website. Making a schematic, symbol, and layout of a 2 input NAND gate with successful DRC and LVS. As the tutorial goes pretty in depth and includes minor details such as settings and parameters, this prelab portion will be an expedited version.
Schematic of a NAND gate with PMOS and NMOS with the same length of 6u.
Symbol view of the above schematic.
Simulation schematic using the NAND gate.
Simulation result.
NAND layout view with successful DRC pass.
Extracted the previous layout and ran LVS with the schematic created earlier, the net-lists match as we can see here. Note: the current settings of LVS ignore the size differences of the PMOS and NMOS. In the schematic, both are set as 6u, but in the layout, the PMOS is set as 12u. Adjusting the following setting is supposed to have the netlists not match, however, in my schematics I still get a clean LVS pass, the details of the LVS say that the NMOS and PMOS used in the schematic are not in the netlists. Not quite sure how to fix that, could be an update to Cadence since Dr. Baker's tutorial was made.
Lab Work
NAND Gate
Adjusted layout for a 6u NAND gate, both PMOS and NMOS are 6u. Clean DRC pass.
Extracted updated NAND, clean LVS pass.
XOR Gate
Schematic view of a XOR gate.
Symbol of the above schematic.
Layout of the XOR gate with clean DRC pass.
Extracted view of the above layout and yielded a clean LVS pass.
Truth table verification
Schematic of gates (NAND, XOR, Inverter) that we will use to verify that these gates satisfy their respective truth tables.
Truth Table:
B A Ai NAND XOR
0 0 1 1 0
0 1 0 1 1
1 0 1 1 1
1 1 0 0 0
Simulation results for truth table verification of gates (NAND, XOR, Inverter) We can see that these do satisfy the truth tables.
Full Adder
Schematic view of a full adder, using the gates I've created.
Symbol view of the schematic.
Layout of the full adder, with clean DRC pass.
Extracted the layout and have clean LVS pass.
Simulation schematic to ensure functionality. The truth table for this should be as follows:
A B Cin S Cout
0 0 0 0 0
1 0 0 1 0
0 1 0 1 0
1 1 0 0 1
0 0 1 1 0
1 0 1 0 1
0 1 1 0 1
1 1 1 1 1
Simulation results. Upon careful examination, we can see the truth table is satisfied.