Laborator 2
module mux_1s_1b(
input d0,
input d1,
input s,
output o
);
assign o=s? d1:d0;
endmodule
module main;
reg d0;
reg d1;
reg s;
wire o;
integer i;
mux_1s_1b u1(
.d1(d1),
.d0(d0),
.s(s0),
.o(o)
);
initial
begin
$display("Hello, World");
$monitor("d0=%b,d1=%b,s=%b,o=%b",d0,d1,s,o);
for(i=0;i<8;i=i+1) begin
#10 d1=i[2];d0=i[1];s=i[0];
end
$finish ;
end
endmodule
1) Proiectati utilizand verilog un multiplexor 2-la-1, pe 3 biti, avand 3 intrari, s,d0 si d1 avand o iesire o.
2) Proiectati utilizand verilog un multiplexor 2-la-1, pe 3 biti, avand 2 intrari s si d si avand o iesire o. Multiplexorul selecteaza fie jumatatea mai semnificativa a intrarii d sau jumatatea mai putin semnificativa, daca s are valoarea 1 sau 0, respectiv.
3) Construiti folosind verilog un sumator modulo-64.
1)
module mux_2_1(
input [2:0]d0, //vector de intrare d0 cu indici de la 2 la 0
input [2:0]d1,
input s, // intrare de selectie(intre d0 si d1)
output [2:0]o // iesire in functie de s,d0,d1
);
assign o = s ? d1 : d0; //daca s este 1 atunci selectam d1, altfel d0
endmodule
module main;
reg [2:0]d0;
reg [2:0]d1;
reg s;
wire [2:0]o;
integer i;
mux_2_1 u1(
.d1(d1),
.d0(d0),
.s(s),
.o(o)
);
initial
begin
$display("Hello, World");
for(i=0;i<8;i=i+1) begin
#10 d1=i[2];d0=i[1];s=i[0];
end
$finish ;
end
always @(o)
$display("d0=%b,d1=%b,s=%b,o=%b",d0,d1,s,o);
endmodule
2)
module mux_2_1_s(
input [2:0]d, //vectorul de intrare
input s, //intrare de selectie
output [1:0]o
);
assign o = s? d[2:1] : d[1:0];
endmodule
module main;
reg [2:0]d;
reg s;
wire [1:0]o;
integer i;
mux_2_1_s u1(
.d(d),
.s(s),
.o(o)
);
initial
begin
$display("Hello, World");
for(i=0;i<8;i=i+1) begin
#10 d=i[1];s=i[0];
end
$finish ;
end
always @(o)
$display("d=%b,s=%b,o=%b",d,s,o);
endmodule
3)
module adder(
input [5:0]x,
input [5:0]y,
output [5:0]z,
output co
);
assign {co,z}=x+y;
endmodule
module test;
reg [5:0]x;
reg [5:0]y;
wire [5:0] z;
wire co;
integer i;
adder uut (
.x(x),
.y(y),
.z(z),
.co(co)
);
initial begin
$display("Hello, World");
for(i=0;i<4096;i=i+1) begin
#10 {x,y}=i[11:0];
end
$finish ;
end
always @(z)
$display("x=%b,y=%b,z=%b",x,y,z);
endmodule