Xilinx XUP VIRTEX-II PRO Development Board

Overview

The Xilinx XUP VIRTEX-II PRO box is plain but has a couple of labels, one of which states 'The XUP VIRTEX-II PRO One Board for the Entire Engineering Curriculum Powered by the VIRTEX-II Pro XC2VP30' with 30,816 Logic Cells DESIGNED BY THE XILINX UNIVERSITY PROGRAM WWW.XILINX.COM/UNIV'. 

There is also a URL for the Xilinx university program:

www.xilinx.com/univ

The link no longer works but can viewed via the Wayback Machine:

https://web.archive.org/web/20100501081913/www.xilinx.com/univ

There is also Digilent branding, as likely they manufactured/distributed it.

A link for the reference materials is on another label:

www.digilentinc.com/xupv2p

That link is also dead and hasn't been archived.

I'll describe what came in the box but keep in mind that since I got the kit second hand some parts may be missing or those that were included weren't originally):

Retractable 'DIGILENT' USB 2 A-B cable
X2 SATA data cables
DE-9 female serial cable
DC 5V 4A centre pos. switching power supply and UK mains lead
Various metal posts and screws
KVR266X64C25/256 256MB DDR Non-ECC RAM (RAM had to be purchased separately so the previous owner must have bought some)
CD titled 'XUP Virtex-II Pro Development System Curriculum-On-A-Chip'
The main board protected by an antistatic bag

The board is labelled as 'VIRTEX-II PRO', 'XILINX Research Labs' and 'XUP VIRTEX-II PRO DEVELOPMENT SYSTEM'. A nice feature of the board is that it has screw blocks for various voltages, for testing and providing power to external circuits. The user guide details how to test the various voltages.

To go into more detail about the development board I'll reproduce the main spec below, as can be found in the user guide (which I'll talk about more shortly):

Xilinx XUP VIRTEX-II PRO Development Board
Virtex-II Pro FPGA with PowerPC 405 cores
Up to 2 GB of Double Data Rate (DDR) SDRAM
System ACE controller and Type II CompactFlash connector for FPGA configuration and data storage
Embedded Platform Cable USB configuration port
High-speed SelectMAP FPGA configuration from Platform Flash In-System Programmable Configuration PROM
Support for “Golden” and “User” FPGA configuration bitstreams
On-board 10/100 Ethernet PHY device
Silicon Serial Number for unique board identification
RS-232 DB9 serial port
Two PS-2 serial ports
Four LEDs connected to Virtex-II Pro I/O pins
Four switches connected to Virtex-II Pro I/O pins
Five push buttons connected to Virtex-II Pro I/O pins
Six expansion connectors joined to 80 Virtex-II Pro I/O pins with over-voltage  protection
High-speed expansion connector joined to 40 Virtex-II Pro I/O pins that can be used differentially or single ended
AC-97 audio CODEC with audio amplifier and speaker/headphone output and line level output
Microphone and line level audio input
On-board XSGA output, up to 1200 x 1600 at 70 Hz refresh
Three Serial ATA ports, two Host ports and one Target port
Off-board expansion MGT link, with user-supplied clock
100 MHz system clock, 75 MHz SATA clock
Provision for user-supplied clock
On-board power supplies
Power-on reset circuitry
PowerPC 405 reset circuitry

The XC2VP30 FPGA has the following features:

13969 slices
80x46 array size
428Kb distributed RAM
136 multiplier blocks
2448Kb block RAMs
8 DCMs
2 PowerPC RISC cores
8 multi-gigabit transceivers

The included CD is simply labelled 'V2P_CD' when viewed on a computer and contains just 74MB of data. The various sub folders and what they contain are:

Documentation: ZIP and PDF versions of the schematic (rev. c) and user guide.
lib: ZIP file containing system files (used by Xilinx Platform Studio system builder to define the XUP VIRTEX-II PRO system)
Quickstarts: ZIP and PDFs for using the system builder
Reference_Designs: various projects including the built-in design
release_notes: PDF release notes concerning the system builder
UCF_Files: various User Constraints Files for the FPGA system

The user guide, called the 'hardware reference manual' within the guide, is dated 2005. I've included some of the information on this page from the user guide as it has key concepts that need to be digested:

The 5V power supply is used to generate 3.3V, 2.5V and 1.5V for the FPGA and on-board peripherals, these voltages also available via the screw blocks. The board can do current measurement and external power can be connected if more capacity needed.

The FPGA can be configured via internal platform flash PROM (which can hold two configurations), internal compact flash (holds 8 configurations), and through platform cable USB or parallel port interface.

Up to 2GB DDR RAM supported, buffered or unbuffered, 64-bit or 72-bit organization (latter to support ECC).

The System Advanced Configuration Environment (System ACE) Controller manages FPGA configuration data.

The FPGA is equipped with a CPU debugging interface and a 16-pin header. This connector can be used in conjunction with third party tools, the Xilinx Parallel Cable IV, or the Xilinx Platform Cable USB to debug software as it runs on either PowerPC 405 processor core.

USB 2 interface is used for programming or configuring the Virtex-II Pro FPGA in Boundary-Scan (IEEE 1149.1/IEEE 1532) mode. Target clock speeds are selectable from 750 kHz to 24 MHz. The USB 2.0 microcontroller attaches to a desktop or laptop PC with an off-the-shelf high-speed A-B USB cable. 

At power up, or when the RESET_RELOAD push button (SW1) is pressed for longer than 2 seconds, the FPGA begins to configure. The two configuration methods supported, JTAG and master SelectMAP, are determined by the CONFIG SOURCE switch, the most significant switch (left side) of SW9.

If the CONFIG SOURCE switch is closed, on, or up, a high-speed SelectMap byte-wide configuration from the on-board Platform Flash configuration PROM (U3) is selected as the configuration source. This is identified to the user through the illumination of the PROM CONFIG LED (D19). 

The Platform Flash configuration PROM supports two different FPGA configurations (versions) selected by the position of the PROM VERSION switch, the least significant switch (right side) of SW9.

If the PROM VERSION switch is closed, on, or up, the GOLDEN configuration from the onboard Platform Flash configuration PROM is selected as the configuration data. This is identified to the user through the illumination of the GOLDEN CONFIG LED (D14). This configuration can be a board test utility provided by Xilinx, or another safe default configuration. It is important to note that the PROM VERSION switch is only sampled on board powerup and after a complete system reset. This means that if this switch is changed after board powerup, the RESET_RELOAD pushbutton (SW1) must be pressed for more than 2 seconds for the new state of the switch to be recognized.

If the PROM VERSION switch is open, off, or down, a User configuration from the on-board Platform Flash configuration PROM is selected as the configuration data. This configuration must be programmed into the Platform Flash PROM from the JTAG Platform Cable USB interface or the USB interface.

If the CONFIG SOURCE switch is open, off, or down, a lower speed JTAG-based configuration from Compact Flash or external JTAG source is selected as the configuration source. This is identified to the user through the illumination of the JTAG CONFIG LED (D20). The JTAG-based configuration can originate from several sources: the Compact Flash card, a PC4 cable connection through J27, and a USB to PC connection through J8 the embedded Platform Cable USB interface.

Four status LEDs show the configuration state of the XUP Virtex-II Pro Development System at all times. The user can see the configuration source, configuration version, and tell when the configuration has completed from the status LEDs:

System Status D19 (Green) PROM Config D20 (Green) CF Config D14 (Amber) GOLDEN Config D4 (Red) Done
SelectMAP USER LOADING ON OFF OFF OFF
SelectMAP USER COMPLETED ON OFF OFF ON
SelectMAP GOLDEN LOADING ON OFF ON OFF
SelectMAP GOLDEN COMPLETED ON OFF ON ON
JTAG COMPACT FLASH LOADING OFF ON OFF OFF
JTAG COMPACT FLASH COMPLETED OFF ON OFF ON
JTAG USB or PC4 LOADING OFF ON OFF OFF
JTAG USB or PC4 COMPLETED OFF ON OFF ON

The board contains a footprint for a user supplied oscillator that can be added as an additional clock source.

As well as the two Digilent peripheral expansion connectors and single Digilent high speed port there are provisions for four user supplied expansion connectors that can be added (Digikey part S2012-30-ND).

Toward the end of the user guide you will find the following Appendices:

Appendix A how to configure FPGA from on-board USB port using the embedded Platform USB Cable.

Appendix B programming the platform flash PROM user area. Two FPGA configurations are supported by the design revisioning capabilities of the Platform FLASH PROMs. The “Golden” configuration is stored in Revision 0 and is write/erase protected, and the “User” configuration is stored in Revision 1.

Appendix C restoring the Golden FPGA Configuration

Appendix D Using the Golden FPGA Configuration for System Self-Test. Tests critical board features and reports on board health and status.

The “Golden Boot” design covers the following elements of the system:

1. Clock presence

2. Push buttons, DIP switches, and LEDs

3. Audio CODEC and power amplifier

4. RS-232 serial ports and PS/2 ports

5. SVGA output

6. 10/100 Ethernet and Silicon Serial Number

7. Expansion ports

8. MGTs

9. System ACE processor interface

10. DDR SDRAM module and Serial Presence Detect PROM

Appendix E covers User Constraint Files (UCF), and Appendix F has Links to the component data sheets.

Getting started and running tests

As mentioned in the Overview section, Appendix D in the user guide talks about the various hardware test that can be performed, which are available as part of the Golden configuration stored in the on-board PROM. 

I plugged the provided 5V power supply into the board and put the power switch (SW11) into the on position. The 2.5V, 3.3V, and 1.5V LEDs lit, the SYSTEM ACE ERROR was rapidly flashing, and the JTAG CONFIG LED was lit.

The first test involves checking the various voltages, however, the guide seemed to have some mistakes, which could be due to different revision of the board, although I've only seen mention of rev. C.

In the guide it says:

"Verify that three Shorting Jumper Blocks are installed in JP1, JP2, and JP3."

This is confusing as JP1 is a block of three connectors but JP2 is a standalone 'disable' connector which turns off 2.5V power, as confirmed later on.

It also says in the guide:

"Connect the negative lead of the multimeter to J35 and the positive lead to J34. The meter should read between 1.425V and 1.575V, and LED D19 “1.5V OK” should be on."

The 1.5V connectors are J29 and J28, the 1.5V OK LED is D5.

Later in the guide we then get mention of JP2 is the 'disable' connector:

"Install the Shorting Jumper Block on JP2, LED D17 “2.5V OK” should be off, and D6 “RELOAD PS ERROR” should be on. Remove the Shorting Jumper Block."

Each of the voltages passed so that was a good sign.

Next I did the Clock, Push Button, DIP Switch, LED, and Audio Amp tests. The first tests passed but when it came to the SVGA Color Output Test I couldn't get it to work, there was nothing displayed on my monitor. It's possible that the board doesn't have the original full test config, however, I found that if SW9 had '1' set to ON (up), and '2' set to off (down) and powered on the board a 'XUP-V2Pro Development System Audio Filter Demonstration' screen appeared on the monitor, showing that at least the VGA output was working.

Next I moved to the 'Processor-Based Tests' section. This makes use of the on-board PowerPC and requires a connection to a PC via serial. A MAX3388E RS-232 Transceivers IC handles the serial port (J11). This is where I had problems. Modern PCs don't have a serial COM port but I have several RS-232 to USB adapters, in particular I've had success with a Waveshare PL2303 adapter. I made up a DE-9 male to female lead carrying GND, RX, and TX. I connected the GND lead to the PL2303 GND and TX lead to PL2303 RX (at this point I was just testing transmit).

The PL2303 has a shunt setting for 5V/3.3V logic, I had it set to 3.3V. Connecting the PL2303 to my Surface Pro (running Windows 10) and opening PuTTY and a serial connection set to 9600 (as specified in the user guide) I powered on the FPGA board but got garbled text, this also happened when I pressed the RESET/RELOAD button. I tried with the PL2303 set to 5V logic but there was no text when powering/resetting the FPGA board. I tried other RS-232 to USB adapters but that also showed no text.

The problem could have been the speed wasn't actually 9600 but I tried several common speeds and got varying amounts of garbled text. I did wonder if the board needed the additional serial connections - RTS/CTS/etc - the user guide however says it doesn't need flow control. I had a look at the transmit pin (FPGA side) using my oscilloscope and saw a very un-square like waveform going between -1/+1V. I thought to try the receive pin (FPGA side) and I got square waves -4.2/+4.2V, which seemed much more like data, and the voltage level matches what is expected of the MAX3388E. Looking at the board schematic, the RX and TX are effectively swapped via the on board MAX3388E and that's is why the user guide says a null modem cable (which swaps RX and TX) isn't required to connect the board to a PC.

Because the voltage is +/-4.2V that makes sense as it was designed to drive a 'real' COM port but that can cause issues with RS-232 to USB adapters. The Waveshare PL2303 not surprising uses a PL2303 IC but looking at the datasheet it's unclear whether it could support -4.2V and I didn't want to risk damaging the adapter. Fortunately I had a module that features an ADM232A RS-232 driver/receiver IC as well as an IDC connector for power (5V) along with RX and TX, and DE-9 female connector for RX and TX swapped. I powered the ADM232A module off the FPGA board's 5V and GND and connected the FPGA's board RX & TX to the ADM232A module which in turn was connected to the Waveshare PL2303, which was set to 5V logic as the datasheet for the ADM232A states a minimum of 3.5V high logic level. Note that the ADM232A can withstand up to +/-30V RS-232 input, MAX3388E up to +/-25V.

With it all connected up and the PL2303 plugged into my Surface Pro I opened up a PuTTY serial connection, now when I powered on the FPGA board I got the expected test menu. However, I found the PL2303 got very hot whenever it was set to 5V logic and even with only a single wire connected - GND or TX - or  both was connected to the PL2303 adapter, whether the FPGA board was on or off. So I switched to a different USB to RS-232 adapter, which happened to use an FTDI chip, and set its logic to 5V using a shunt. That worked and the chip didn't get hot.

I will now briefly go through each of the tests available through the serial port. Note that the test names used in the user guide differ somewhat to the names in the actual test menu. First, a look at the self test menu:

The first test (1) tests the SATA ports, in the user guide it's called 'MGT Serial ATA Test'. The user guide explains how to attach a SATA cable to create a loopback via two of the SATA ports (host and target) of the FPGA board in order for the test to work. With the SATA cable connected, '1' can be pressed in PuTTY and then you can choose whether to run a loop test on SATA0 and SATA 1, or SATA2 and SATA1. I was pleased to see the tests passed.

Here is an image show the result of the SATA0 and SATA1 test having passed:

Unfortunately, test (2), EMAC Web Server Test as the user guide calls it, I couldn't get to work. I tried a crossover cable, I tried connecting directly to the router my computer was also connected to but it wouldn't find the webserver hosted by the FPGA board.

For the third (3) test, AC97 Audio Test, there are 3 options:

The user guide explains how to connect up so that you can test passthrough, loopback and game sounds by use of an audio cable, audio source, and headphones/speakers. I had no problems with getting that example working but as warned in the guide be careful if using headphones as the audio is very loud.

For test four, (4) the System ACE Test, it requires a CF/Microdrive to be inserted into the CF slot, which shouldn't contain an FPGA configuration file otherwise the FPGA will be reconfigured. Although I inserted a CF (12MB) that fits that criteria when I powered on the FPGA board it was interesting to see the SYSTEM ACE ERROR LED no longer flashed.

You can see the results of the test as follows:

For test five, (5) DDR SDRAM Test, since a RAM stick was included with the FPGA kit when I bought it I inserted that into the DDR slot (with the board powered off, of course). The test does take a few minutes to complete but it passed:

Finally, test six (6) Expansion Port Test, generates a 20ns pulse with 1.6uS period on each bit in the 80-bit expansion bus, an oscilloscope can be used to ensure that each bit is working. As warned in the user guide and when running the test, do not have any expansion boards plugged in. I probed each of the signal connections on the four unpopulated connectors J1-J4 to make sure the signals were being generated, but you can also check the populated expansion connectors too to ensure they are connected correctly.

At this point most of the system components have been tested.

Loading a new configuration

We will now look at loading a different FPGA configuration to the board via USB. Looking at page 21 of the user guide we can see:

"If the CONFIG SOURCE switch is open, off, or down, a lower speed JTAG-based configuration from Compact Flash or external JTAG source is selected as the configuration 

source. This is identified to the user through the illumination of the JTAG CONFIG LED (D20). 

The JTAG-based configuration can originate from several sources: the Compact Flash card, a PC4 cable connection through J27, and a USB to PC connection through J8 the embedded Platform Cable USB interface.

If a JTAG-based configuration is selected and a valid configuration file is not found on the Compact Flash card by the System ACE controller (U2), the SYSTEMACE ERROR LED (D11) flashes, and the System ACE controller connects to an external JTAG port for FPGA configuration.

The default external source for FPGA configuration is the high-speed embedded Platform Cable USB configuration port (J8) and is enabled when the System ACE controller does not find configuration data on the storage device."

So we need to put the CONFIG SOURCE (left side of SW9) down and we should see JTAG CONFIG LED (D20) lit when the board is powered on. We can then plug a USB cable into the board's USB connector (J8) and your PC, and power on the board.

On the included CD with the kit there are a number projects in the Reference_Designs folder. As as a simple test example we can look at the xup_bsb_onewire project. Copy it from the CD and extract. If you look in the doc subfolder you will find xup_bsb_onewire_release_notes.doc, but because it contains images it can't be opened in Notepad or WordPad, but you could open in Google docs, for example. The doc informs us that the project accesses the software silicon serial number and displays it via rs-232. The doc goes on to explain how to open up the project in Xilinx Platform Studio. While it's good to do so to learn how the project works we can for now just configure the board with the already generated .bit file, testapp_onewire.bit, which can be found in the bitfiles sub folder. To do so we can use iMPACT (part of ISE Design Suite), which I happened to already have on my computer.

Open up iMPACT (you'll need to install it if you don't already have it) and if prompted to load the last project click the No button. When it asks if you want the system to automatically create and save a project file select the Yes button. In the next window it should have selected 'Configure devices using Boundary-Scan (JTAG)', click the OK button. It should detect the cable, if not you'll need to install a driver - check Device Manager to see if there are any issues. Make sure you're using a decent USB cable, the Diligent one that came with the kit didn't work for me.

You'll get a pop up asking if you want to configure and assign configuration fields, click the Yes button. Firstly it will ask for a .mcs/.isc/.bsd file so click the Cancel button, then it'll ask for a .mpm/.bsd file, again click the Cancel button, then it will ask for a .bit/.rbt/.nky/.isc/.bsd file so navigate to and select testapp_onewire.bit. If iMPACT crashes (which it usually does if running on modern Windows) then copy the .bit file to whatever the default folder when prompted for the config file, then open up iMPACT and try again. Once the .bit file is selected you'll be given a summary of the device properties of the three devices found in the chain - the PROM (xcf32p), ACECF (xccace), and FPGA (xc2vp30). Click the OK button. You should see in the chain that xcf32p and xccace are set to bypass as we aren't configuring/programming them and xc2vp30 has testapp_onewire.bit associated with it.

Before we configure the FPGA we need to connect the board's RS-232 port to your PC and open a serial connection using a terminal program, such as PuTTY, set to 9600. In iMPACT right-click the xc2vp30 icon and select Program. In PuTTY should see the board serial number displayed. If you press the RESET\RELOAD button the serial number will be displayed again. If you power off and on again the serial number won't display again since we only configured the FPGA temporary, we didn't program the PROM.

This was a very simple example but provided it worked it's another good sign the board is working and that we can configure it with other bit files.

Using the Base System Builder wizard

This section is a bit longer than perhaps it should be as I had difficulty running some software but it's worth reading through as a learning exercise. In short, you need to use Windows XP either in original form or through a Virtual mMchine (VM).

Initially I thought I could open the projects on the CD in ISE Design Suite so I did some research and found that the XC2VP30 FPGA was apparently last supported in ISE 10.1.3. However, I discovered that the projects on the CD were made in Xilinx Platform Studio (XPS), so you would need an old version of that. Additionally, if you want to use the Base System Builder wizard, which makes it easier to target the FPGA board, you will need to use XPS. Although I already had V14.7 installed it is not compatible with the FPGA board even if you point it to the library folder (found on the CD), as detailed in Release_Notes_Base_System_Builder_for_XUP.pdf and XUPV2P_Base_System_Builder.pdf (both found on the CD).

One solution is to get the Embedded Development Kit (EDK) 7.1i from the ISE archive:

https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive-ise.html

Note that you will need to sign in and fill in a form (the download starts instant so it's not like someone has to check the details you supplied before you can download). However, you do need to click on the 'Obtain a Registration ID' link on the downloads page, which will require filling in and submitting another form. You will then be emailed with a link taking you to a page with the required ID.

You can then launch the XPS except when I tried (note: running on Windows 10, the software was designed for XP) I get error:

$XILINX does not point to an ISE 7.1 installation

Which is strange as during the install it supposedly sets the path correctly. So I switched to using an Oracle Virtual Machine (VM) running win 7 I happened to have and installed EDK 7. Note that the installer won't work from a shared folder set up in the VM since it has issues with what it considers is a network drive. After installing EDK 7 and starting XPS I got error:

The program can't start because MSVCR71.dll is missing from your computer.

It appears this is due to not having Visual C++ Redistributable installed so I tried to install it but that failed. So I had to install a certificate:

https://stackoverflow.com/questions/47176239/a-certificate-chain-could-not-be-built-to-a-trusted-root-authority/60812129#60812129

Then I was able to install the Visual C++ Redistributable but that didn't fix the missing DLL issue so I downloaded the DLL and added it to the C:\Windows\SysWOW64 folder folder. Now when I ran XPS it said:

Environment variable XILINX is not set

If we look at the environment variables (search for environment variables in start menu and click 'Edit the system environment variables' then click 'Environment Variables...' button) indeed there was no XILINX entry under the System variables section. I clicked New... button, added XILINX as Variable name and for the Variable value put C:\Xilinx, since that was where EDK 7 was installed. Note that I had to also edit the environment variable under user variables as well. Now when I tried to open XPS I got an error about not finding libPortability.dll.

Apparently the issue is actually because you also need ISE 7 installed but the only other option I could find under 7.x was the 'Programming Tools' but that didn't help - by the way, I did so under Windows 10, not in the VM.

As a last attempt, I tried the next version up, downloading and installing 'ISE Foundation - 8.2i  Full Product Installation' and then 'Embedded Development Kit - 8.2i  Full Product Installation'. The readme for EDK warns you need SP1 so I downloaded and installed that before installing EDK. After installing EDK I launched XPS and it worked. So perhaps EDK V7 just needed SP1 installed before EDK but even though it was a long way to get EDK working it's better to have a latter version which still supports XC2VP30. However, dialog boxes and such may differ from V7.

Looking once again at Release_Notes_Base_System_Builder_for_XUP.pdf I could now follow through. As soon as you launch EDK it has Base System Builder wizard selected so can just select the OK button. Next, enter a project file name, which can also include a path otherwise it uses the current directory, if selecting a folder through the browse button causes the app to crash, which it does for me running Windows 10, enter a name/path manually in the provided box.

Click the checkbox for 'Use Repository paths' and browse to and select the lib folder copied from the CD - make sure it's located on the C drive rather than Documents, for example, otherwise there may be issues. Then you can click the OK button. The next options that appear let you either create a new design or load an existing .bsb settings file, I went with the coption to create a new design. Next, we have the option to select a board, which needs to be 'XUP Virtex-II Pro Development System'. The only option for Board revision is 'C' so it has to be left at that. Click the Next button to progress. On the next page it lists at the top the architecture/device/package/speed grade. There is an option to select between 'Micro Blaze' (soft processor) and PowerPC (hard processor):

So this means you have to have a processor in the design, likely because certain periperhals will need it. Likely if you don't actually make use of the processor it will just be put in an ideal state. Since Micro Blaze takes up logic on the FPGA you should only select it if you actually need to use such a processor.

The next page lets you set clock, debug and memory options, following that I/O options can be configured spread across multiple pages. There is also a page to select what behaves as stdin/stdout, wich would come in handy for debugging, etc., and a couple of C test applications can be included. When you get near to the end you can click the Generate button, which will take you to the final page, which lists the various project files and the Finish button can be clicked:

A pop up will ask you ('The Next Step') what you want to do next, although I selected 'Download the design to a board' it opened the project in XPS:

The various components of the assembly view can be expanded and you can also click on the Ports and Addresses radio buttons to get further information.

There is also a block diagram view (click BLOCK DIAGRAM tab) but it appeared very small seemingly without no option to zoom in.

The options in Device Configuration were greyed out, which I thought was because the board wasn't connected but it seems to happen when the app is busy, relaunching XPS the options were enabled. When launching XPS, an existing project can be opened by selecting 'Open a recent project', select the project from the drop-down and click the OK button. To download the bitstream: Device Configuration->Download bitstream.

However it seemed to be taking forever (the process progress blue wheel bottom left just kept turning) and it really slowed down my computer.  After almost 10 minutes the program crashed and took the whole computer down. I tried multiple times but each time it crashed my computer. I even tried to export the project to ISE but the system crashed before it finished. While I could try using the VM, I'd already spent a lot of time trying to get the builder to work - ideally I needed a computer running Windows  XP as that's what the software was designed for.

Another option would be to create a project from scratch in ISE and certainly I could copy the project files for a particular example project from the CD to a new project, however, it is really helpful to have XPS working, since it deals with a lot of the complexity of using the FPGA board. So, returning to the virtual box I created a new machine and installed Windows XP with SP3, which in hindsight, I should have done from the start. Then I installed ISE Foundation 8.2i, ISE SP1, and EDK 8.2i, EDK SP1 (which I hadn't noticed prior).

Opening up XPS within the VM I once again went through the steps of using the Base System Builder wizard to create a project for the FPGA board. When it had finished and I had the option to go into XPS I went to Device Configuration->Download Bitstream. This time it was actually doing something, I saw feedback in the log window as it went through the various phases, so that shows running outside of the VM in Windows 10 it was definitely having issues. But in the VM running Win XP, the O/S the software was designed to run on, it works fine. In total XPS took about 5 minutes to complete the Download Bitstream, although at this point I didn't have the board connected, just in case the software failed.

In the following screen you can see XPS having finished building the project. Note the cable error because I didn't have the FPGA board connected.

You can also see top-right I have opened several of the C source files that run on the PowerPC, these test programs can also be added while using the Base System Builder wizard. In Windows 10 outside the VM I couldn't even open the source files in XPS.

To be able to download the config to the FPGA board while using the VM we need to add a USB filter otherwise Windows will 'grab' the hardware before the VM can use it. If using Oracle VM, with the VM powered down, open its settings and select USB. Click the + icon to add a USB filter and select XILINX and click the OK button. Unplug the FPGA board, start the VM, when XP gets to the desktop plug in the board. Windows will pop up with the 'Found New Hardware Wizard' and ask if it can connect to Windows Update, which I said Yes, even though it'd probably do no good. On the next page it asks whether to install the software automatically or install from a list or specific location. I went with the former option and it installed the device. Under device manager it shows up as 'Xilinx Platform Cable USB'.

I reopened XPS and reloaded the project and once again went to Device Configuration->Download Bitstream. Since it had previously built the project it went straight to downloading the bitstream, which took less than a minute. In PuTTY (which I ran outside the VM) it displayed:

-- Entering main() --

-- Exiting main() --

That is I believe the TestApp_memory.c running which just prints the above text since it can't test the RAM that the test program is running on. I didn't quite understand how the RAM is configured when using the Base System Builder so that is something I can experiment with to actually get it to test the RAM. However, the peripheral test program doesn't run, which is something I'll get to shortly.

To debug go to: Debug->Launch Software Debugger... It will then pop up asking which app you want to debug, in my case TestApp_Memory or TestApp_Peripheral. Then the code will show up in a window:

From the window's menu we can can call up the stack, registers, watch expessions, local variables, etc. But as prompted we must run the program first, either clicking the Run icon or via menu Run->Run. A Target Selection pop-up appears, I left the options as they were and clicked the OK button. Unfortunately that didn't work and there was no other selection for Target other than Remote/TCP.

So I tried Debug->Launch XMD... A pop-up will ask you what processor (core), I went with ppc405_0. It then poppped up with XMD Debug Options. For connection type it was set to Hardware and I left the JTAG properties at default and clicked the Save button and it opened a command line window and opened up a connection. I then realised I could do Debug->Launch Software Debugger... again and this time it had the TCP connection. The debugger ran and stopped at the start of main(). In the following image you can see the debugger running with the Registers and Breakpoints windows opened:

We can now step through the program using either the icons or through the Control menu. Note that 'Next' is equivalent of 'step over' in other debuggers.

After closing the debug session I did try debugging with TestApp_Periperhal selected but it was empty.

In the user guide page 16 they also have two apps, memory and peripheral, and they explain how to enable/disable each program. The memory app is enabled so you have to right-click on Project: TestApp_Memory in the Applications section of Project Information Area and select 'Mark to Initialize BRAMs', which will remove the check. Then right-click on Project: TestApp_Peripheral and do the same, which will add a check next to 'Mark to Initialize BRAMs'. Unlike in the user guide there was no need to uncomment any code, however. Then we have to build and download again: Device Configuration->Download Bitstream, which was very quick. This time we got some different text, showing that TestApp_Periperhal was indeed running:

Running GpioOutputExample() for LEDs_4Bit...

GpioOutputExample PASSED.

Running GpioInputExample() for DIPSWs_4Bit...

GpioInputExample PASSED. Read data:0xF

Running GpioInputExample() for PushButtons_5Bit...

GpioInputExample PASSED. Read data:0x1F

-- Exiting main() --

Note: the peripheral test appears to just check that it can initialize the input/output drivers for the LEDs and switches.

If we want to launch the debugger to step through the test peripheral code we can now, selecting TestApp_Peripheral when prompted.

So, using a VM running Windows XP I was able to create and test a project made with Base System Builder. Having used old FPGA boards previously I had had success using Windows 10 as buggy as ISE is running under a modern Windows O/S. But with Base System Builder you really do need to use Windows XP, emulated or otherwise, and at least it runs smoothly and is quick despite running in a VM, as I put it on 'high' hardware settings.

Troubleshooting

DIMM memory errors

https://www.eecg.toronto.edu/~pc/courses/edk/node2.html

Note: many of the links on the page no longer work but the information regarding memory errors may be of use.

All content of this and related pages is copyright (c) James S. 2024