Digilent Nexys 3

The Board in Detail

A summary of the key features are:

FPGA

XC6SLX16-1CSG324C

I/O Interfaces

USB-UART for programming and serial communication

10/100 Ethernet

8-bit VGA output (3R, 3G, 2B)

USB HID Host for mice, keyboards and memory sticks

Memory

16 Mbyte CellularRAM

16 Mbyte SPI (quad mode) PCM non-volatile memory

16 Mbyte parallel PCM non-volatile memory

Displays

4-digit 7-segment display

Switches and LEDs

8 Slide switches

8 LEDs

5 Push-buttons

Clocks

100 MHz oscillator

Expansion ports

4 Pmod ports

40 pin High-Speed Expansion port

The board lists the component and signal names for each component, for e.g., SW7 and T5, making it easier when mapping the I/O of a design to the FPGA pins.

Going into more detail about the various components: along one edge are power switch SW8 (sliding type), micro USB for programming/power in J3, unpopulated connector JP6 (behind 24MHz crystal X1), ethernet socket J9, VGA J2, BUSY LED LD12 and USB HOST J4 (type-A male). Along another edge we have J12 and J6 (unpopulated) and 8 sliding user switches (SW7 to SW0). Depending on what position the switches are in they either connect the associated signal to ground or high through a 10KΩ resistor. The resistor protects the FPGA should a signal that's connected to a switch be incorrectly configured as an output as to avoid a short that could damage the FPGA.

Additionally, there are 8 user LEDs (LD7 to LD0) and 5 momentary push button user switches arranged in a cross pattern (BTNL, BTND, BTNS, BTNR and BTNU). When pressed, each button pulls the associated signal to ground, when released the signal is pulled high through a 10KΩ resistor. There is also a 4-digit, multiplexed, 7-segment LED display above the switches (TYPE KW4-281ASB).

Along the third edge is a USB micro UART, J14 (unpopulated, has 6 connections), two LEDs LD0 and LD1, high density connector J1, JP4 VUEXP (unpopulated), and J7 6-way header for JTAG. As for the last edge there are PMOD connectors JD1, JC1, JB1 and JA1, JP1 3 way header for selecting between USB/wall adapter, with power good LED LD8 behind it (indicates if the connected power supply is suitable), barrel jack power connector J10 with 2-way power header J11 behind it.

Also on the board are momentary switch RESET BTN5 (reset FPGA configuration memory), JP8 BANK 0 POWER 3V3/2V5 3-way header, J5 unpopulated 6-way, JP7 HSWAP 2-way unpopulated, and J8 MODE M0/M1 2 x 2-way headers for configuration and LD9 DONE LED. The configuration mode options are as follows:

M1 M0 Configuration Mode

0 0 BPI

0 1 SPI - on board SPI flash

1 0 ---------

1 1 Slave Serial - USB Memory

The DONE LED will illuminate when the configuration has been loaded from the non-volatile memory after power on and also when any programming sent to the board has finished and will stay illuminated until the board programmed again.

As for the chips on the board some of them vary from the official schematic but likely substitutes have been used and there is also the issue that sometimes manufacturers don't use the full part number on an SMD package. On the top of the PCB we have:

DCP1027 IC9 100MHz oscillator (DCS8001 on schematic).

P5Q128A1 IC6/IC7 (IC6 and IC7 are the same but different package, one or the other is used) 128-Mbit, Quad/Dual/Single Serial Interface, 128-Kbyte Sectors Phase Change Memory (PCM) with 66MHz SPI Bus Interface. This is the 'SPI' memory.

XILINX SPARTAN-6 XC6SLX16 CSG324CIV1101 IC8 Spartan-6 series Field Programmable Gate Array.

P8128A13T176 IC10 PCM (PRAM) Memory IC 128Mb (16M x 8) Parallel, SPI 115 ns (NP8P128A13T1760E on schematic). This is the 'BPI' memory.

0WA47 PW510 IC11 PSRAM (Pseudo SRAM) Memory IC 128Mb (8M x 16) Parallel 104 MHz 70 ns (MT45W8MW16BGX on schematic). This is the 'Cellular RAM'.

1B3633N3538 IC13 Buck Switching Regulator IC Positive Adjustable 0.6V 2 Output 3A (LTC3633EUFD#PBF on schematic).

LFKMN018926 IC14 Switching Voltage Regulators 400mA/800mA Synchronous Step-Down DC/DC Converter with Average Input Current Limit (LTC3619IDD#PBF on schematic).

Additionally, there is Xilinx, Micron, Linear technology, Cypress Perform and DIGILENT Beyond Theory branding, and the board name NEXYS 3.

On the bottom side we have:

8MHz crystal X2

CY7C68013A-56 IC1 High-Speed USB (USB 2) Peripheral Controller.

PIC24FJ192GB106 IC2 General Purpose USB Microcontroller. For the USB HID Host.

FTDI FT232R IC3 USB Full Speed to Serial UART IC. For the USB-UART Bridge (Serial Port) interface.

4LC1037 IC4 16K x 8 I2C compatible EEPROM (24AA128 on schematic). Contains the code for IC1 (USB controller) to load into its RAM.

SMSC 8710A-EZK IC12 10/100 Ethernet Transceiver.

We also have a ‘Produced in Association With Shanghai Jiao Tong University’ with the logo.

The use of PCM (phase-change memory) chips means faster operation as there is no need for block erase as is required with typical flash memory.

The board can either be powered via the USB 2 micro port marked ‘USB PROG’, in which case JP1 must have its shunt set to the ‘USB’ position, or via a wall adapter using the 2.1mm (internal diameter) barrel plug (5V to 5.5V, centre positive, 5W), provided JP1 is in the ‘WAL’ position. An external power is usually used when either more power is needed than USB can supply (such as when connected to a PC) or if the board is to be operated independently from a PC. External power can also be connected through J11, which is in parallel with the barrel plug, so use only one or the other if not using USB. Switch SW8 controls power to the board but note that it only enables or disables the on-board regulators so to completely stop power being drawn remove the power supply (even when the power switch is off power will still be provided to the USB HOST J4 connector).

FPGA configuration can be written to either PCM chips with the mode selection J8 on the board determining from which chip the configuration is loaded at boot. As the configuration only requires 512KB of memory, the remaining space in the PCM chip can be used for user data.

At manufacturer, the SPI PCM device is set with a configuration that is used to test the board before being shipped but of course can be overwritten as needed. The BPI PCM device is written with a configuration with a demonstration program for the user to do their own testing or get to know the basic features, and this requires that the mode jumper J8 is set to BPI mode before power is applied for the demo to run.

The USB-UART (serial port) provides a bridge for communication with a PC using Windows COM port commands provided the USB-COM port drivers are installed (which can be found at www.ftdichip.com under the "Virtual Com Port" or VCP heading).

The USB HID Host allows connection of USB mouse or keyboard but with no support of a HUB so you can only have either a mouse or keyboard connected at any time. A USB flash drive can also be used but only to program the FPGA by having a .bit programming file in the drive's root directory and place a jumper on both M0 and M1 of J8.

Here is a quick reference for the main I/O pin mapping with the component name on the left and the FPGA signal name on the right:

LEDs

LD0=U16

LD1=V16

LD2=U15

LD3=V15

LD4=M11

LD5=N11

LD6=R11

LD7=T11

7-segment Display

CA=T17

CB=T18

CC=U17

CD=U18

CE=M14

CF=N14

CG=L14

LOC=M13

AN0=N16

AN1=N15

AN2=P18

AN3=P17

Slide Switches

SW0=T10

SW1=T9

SW2=V9

SW3=M8

SW4=N8

SW5=U8

SW6=V8

SW7=T5

Push Buttons

BTNS=B8

BTNU=A8

BTNL=C4

BTND=C9

BTNR=D9

First Steps

The board is manufactured with a built-in self test that counts up on the 7-segment displays, turns the individual LEDs on/off in response to the user switches, turns off digits when user buttons are pressed, displays an image through the VGA port, and additionally supports a mouse connected to USB port J4 for further interaction. The demo supposedly can be downloaded from the Digilent website but I have been unable to find it but if you do want it then the following post will be of use:

https://forum.digilentinc.com/topic/3234-nexys3-spartan6-preloaded-designs/#comment-11690

A link is provided to the source code along with the VHD code.

The Adept software allows for basic testing of the Nexys board as well as being a means to program it, you can download it from:

https://digilent.com/reference/software/adept/start

Note that to download Adept you need to answer a short survey.

With the Nexys 3 connected to your PC, run Adept and it should detect the Nexys3 and identify the FPGA as XC6SLX16 as follows:

On the Test tab you can run a RAM/flash test (see below), which will cause anything running on the Nexys3 to stop while the test is being done and Adept will report the RAM, SPI flash and BPI flash types.

Full memory tests can be run from the Memory tab. Oddly, Adept wouldn’t let me run the peripherals test as the Start peripherals test button doesn't appear (as can be seen from the screenshot above, some information is cut off) so either the program isn't running correctly or possibly it is reliant on some software component being on the FPGA, such as is the case for the preloaded design (which my board doesn’t have since the previous owner put their own design on it).

The ISE (Integrated Synthesis Environment) design suite from Xilinx is the software that is used to create FPGA designs, synthesize ('compile'), test and ultimately generate a programming file that can be sent to an FPGA to configure it to run your design. While ISE was superseded by the Vivado design suite, also from Xilinx, it supports Spartan series 7 and up only, thus ISE must be used for Spartan-6 and older. Unfortunately, since the low level workings of Xilinx devices aren't known outside the company it's difficult for others to produce alternative software.

The WebPACK version of ISE is free but has some limited features and you can read about what is included at:

https://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html

There is also a link on that page for downloading ISE.

To download ISE you must have a Xilinx account, which you can create for free, but it does require address verification (for me I had no issues so I’m not sure what is actually involved in the checks as it was automatic and quick). Since I am running Windows 10 I opted for version 14.7 (Windows 10) which is 15.5GB, and tried installing it, only to realise that it creates a virtual machine instead of running natively (apparently, there are ways to make it run natively) but even if you do go with the VM install you need to have a PC set up for VMs (virtualization options enabled in BIOS) as well as have a virtualizer running.

So I tried instead the version listed as ‘Full Installer for Windows 7/XP/Server’ (14.7, October 2013) and after it downloaded I extracted it (using 7-zip since it’s a .tar file) and then ran xsetup.exe to install the software, making sure to select ‘ISE WebPACK’ on the ‘Select Products to Install’ page. After the installation, which includes several other software components that need to be installed, you will be presented with the ‘Xilinx License Configuration Manager’ window: select ‘Get Free Vivado/ISE WebPACK License’ and follow the instructions. You will be taken to the Xilinx site and will need to log in and choose ‘ISE WebPACK License’ when asked to create a new license file which will then be emailed to you so you can use the file to set the license along with instructions to set the license. However, trying to load the license using the Load License... button caused the License Manager window to vanish and although I could use ISE it would shut down if trying to open a file and I could perform certain operations as it would prompt for the license again and trying Windows' built-in compatibility options didn't help.

After looking online the simple solution I found was to run the 32-bit version of ISE (I was using the 64-bit version since my computer is 64-bit) and I was able to set the license and use ISE without it crashing. The main advantage of the 64-bit version of ISE is that it can use more of the computer's available RAM than the 32-bit version and the 32-bit version has the advantage (other than not crashing!) that it will run faster than the 64-bit version going by what Xilinx says:

https://support.xilinx.com/s/article/24127?language=en_US

However, there is no guarantee that on your system you will not have problems running the 32-bit version on a 64-bit computer just because the workaround has worked for my computer.

Now that I had ISE running I created a few simple designs and fortunately the process was familiar having had experience with Altera FPGAs and the equivalent of ISE, Quartus Prime. Note that there is no support for whitespace in file names or object names, use underscore or a dot instead. Because I'm using ISE 14.7 there is no built-in support for the Nexys3 board which only means that certain information has to be entered manually. For example, when a new project is started for the project settings I put the ‘family’ as Spartan6, the device as ‘XC6SLX16’ and the ‘package’ as CSG324 (speed should be -3 if not already set as that).

The following screenshot shows a project I created in ISE which simply turns on and off the 8 user LEDs in a binary pattern while making use also of two sliding switches, one to set whether the LEDs count up or down, as well as another switch to enable or disable the counting. Additionally, a push button switch lets the user reset the count, synchronized with the counter:

While very simple, the design shows a good example of the building block approach in schematic form, alternately code can be written to also generate a design, I just find the schematic approach easier to work with as much as I like to code. The design takes the 100Mhz clock (Main_CLK) and divides it up using a counter (binary_counter_simple) which was created using the Core Generator tool (Tools->Core Generator...), as can be seen below, letting use customize the various specifics of a component such as a counter.

I actually needed far less outputs on the counter but did a miscalculation, however, the design works as I'm only using one of the counter's outputs. This is accomplished using a buffer (BUF), which effectively bridges a single wire to the counter's output bus (please see the Tips section for a video showing more detail how to do it). This wire is connected to the clk input of the second counter, binary_counter, which was also created using the Core Generator tool. This counter has just 8 outputs and lights the LEDs to form a binary counting sequence. The last thing to mention is the inputs to the counter which set whether the count increases or decreases, if the count should be enabled or disabled, and to reset the count. These inputs, along with the outputs, are assigned to actual pins on the FPGA at a later stage in the design process.

An overview of the typical steps to create and program a design using ISE is as follows:

1. Start a new project including specify FPGA type.

2. Create/open sources (Schematic/Verilog, etc.) as needed.

3. Run simulation (ISim)*.

4. Create User Constraints File (Plan Ahead).

5. Synthesize (XST)

6. Implement design (translate, map and place & route).

7. Generate Programming File.

8. Connect FPGA board to PC and power on.

9. Program (iMpact).

*Optional.

Please see the Resources section for more design information including tutorials.

Resources

Select guides for some IP Core Generator components

Binary Counter v11.0

https://www.xilinx.com/support/documentation/ip_documentation/counter_ds215.pdf

Clocking Wizard v3.3

https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v3_3/clk_wiz_gsg521.pdf

Design examples (ZIP download with simple example)

https://www.xilinx.com/content/dam/xilinx/support/documentation/university/XUP%20Boards/XUPNexys3/documentation/Nexys3_EDK_GPIO_UART_AXI-14-4.zip

Development of a robot toy module

https://dournac.org/info/nexys3_n7

Getting Started with FPGA tutorial

https://digilent.com/reference/learn/programmable-logic/tutorials/getting-started-with-fpga/start

Half-Adder TUTORIAL using ISE 14.6

http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/XILINX_TUTORIALS_dr/ISE_dr/ise_schematic_halfadder_NEXYS3_SOE.pdf

How to Create & Simulate New Project in Xilinx ISE Design Suite

ISE In-Depth Tutorial

https://www.xilinx.com/support/documentation/sw_manuals/xilinx13_3/ise_tutorial_ug695.pdf

Reference manual (PDF)

https://www.xilinx.com/content/dam/xilinx/support/documentation/university/XUP%20Boards/XUPNexys3/documentation/Nexys3_rm.pdf

Non-PDF version of the reference manual

https://digilent.com/reference/programmable-logic/nexys-3/reference-manual

Schematic rev. B

https://www.xilinx.com/content/dam/xilinx/support/documentation/university/XUP%20Boards/XUPNexys3/documentation/NEXYS3_sch.pdf

Spartan-6 FPGA Clocking Resources user guide

https://www.xilinx.com/support/documentation/user_guides/ug382.pdf

Tutorial: Xilinx ISE 14.4 and Digilent Nexys 3

https://my.ece.utah.edu/~kalla/ECE3700/ISE-Tutorial_Nexy3_Full.pdf

Tutorials for ISE/WebPACK Version 14.7 Schematic Capture

http://xilinx.eetrend.com/files-eetrend-xilinx/forum/201703/11153-29116-ise_tutorial_14x7_schem.pdf

Tips

Instructions on how to test Digilent Nexys 3 board (download):

https://nanopdf.com/download/instructions-on-how-to-test-digilent-nexys-3-board_pdf

By default the tools configure all unused I/O pins with a weak pull-down on them.

I/O should always be set to LVCMOS33 as the I/O standard setting in the PlanAhead tool for each signal pin you use as to be compatible with the Nexys 3 board.

Xilinx Schematic Editor - Connect IO Marker to bus of different length:

There isn’t an IP core for VGA but it can be handled using the AXI4-Stream to Video Out and the Video Timing Controller (note: registration required). These document will help get you started:

AXI4-Stream to Video Out v2.0

https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v2_00_a/pg044_v_axis_vid_out.pdf

Video Timing Controller V6.1

https://www.xilinx.com/support/documentation/ip_documentation/v_tc/v6_1/pg016_v_tc.pdf

Using the specialist controller modules can prove difficult especially for beginners as there's a lot to get your head around but it isn't too difficult to drive the VGA signals directly using simpler techniques, in which case it would be best to read up on the VGA signals and see if you can implement a controller yourself.

V10 (GCLK) is the 100Mhz clock that is fed into the Spartan-6.

Other FPGA Boards

I have had experience with other FPGA Boards including:

DE1-SoC (Altera)

All content of this and related pages is copyright (c) James S. 2022