The DE1-SoC

The Board in Detail

I got my DE1-SoC second hand (supposedly unused, however) and the box was not in the best shape and the power supply is absent, which is not a big deal as it's just a 12VDC 2A supply. As well as the power supply and the board you would normally get in the box a quick start guide, type A to B USB cable (for programming via the USB blaster built-in to the board), type A to mini-B USB cable (for UART communication).

Here is a top-down view on the board:

As you can see the board is packed with connectors, switches and lights, and with the Cyclone V chip in the centre. Notice that there is a piece of acrylic attached to the board which protects parts of the board that you typically won't need to get to.

On one side of the board (below) from the left is an unpopulated JTAG connector (JTAG is accessible via the on-board USB blaster so a physical connector generally isn't needed), and to its right is a PS/2 connector that accepts either a keyboard or mouse (with a 'Y' splitter cable a mouse and keyboard can be used at once). Next along is a USB socket for the integrated USB blaster, the power supply connector, the power switch and analog input connector.

Looking at another side we can see the various switches up close that can be used to interact with the Cyclone as well as six LED 7-segment displays for displaying simple information.

There are also three smaller switches (warm reset, ARM reset and ARM user button), a user LED and an infrared transmitter and receiver, allowing the board to both emulate a remote control as well as respond to a remote control.

Rotating the board again we have a small 2x7 LTC expansion header, two large 2x20 GPIO expansion connectors (for daughter boards or just general I/O) and a micro SD card which can be accessed by the ARM processor.

On yet another side we have a mini USB socket for UART, two host full size USB ports, Gigabit ethernet for the ARM, VGA output, composite input and sockets for line out, line in and microphone in.

There are a number of revisions of the DE1-SoC board and details of how to find the version you have can be found at:

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=886

The site also lists the differences between the various revisions.

On the underside of the board where the first female USB-A port is located there is a serial number (which may be in blue above a white string of characters) with the last two characters specifying the revision. On my board the characters are 'F0' so it is revision F.

First Steps

The DE1-SoC board comes pre-programmed with a configuration that will do the following when the board is powered using the supplied 12V power supply:

The 7-segment displays count quickly in hex (0 - f).

The red LEDs blink in sequence.

A colour picture of the DE1-SoC board will be shown on a monitor connected to the VGA port (see image below).

With a speaker connected to the line-out jack and the KEY[1] is pressed, a 1 kHz humming sound will be heard. 

Since you need Quartus II to program the DE1-SoC I downloaded the recommended version, V16.0, and opted for the lite edition as it's the free version but has less device support. I downloaded from Intel's site:

https://www.intel.com/content/www/us/en/programmable/downloads/download-center.html

Note that you need to be registered to Intel's site to download files but registration is free (at the time of writing this article).

Select version 16.0 and click on 'lite edition' by the download icon and you will be taken to another page 'Quartus Prime Lite Edition' (since Intel acquired Altera the software is now called 'Quartus Prime').

As to minimize download size I clicked on 'Individual Files tab' and downloaded 'Quartus Prime (includes Nios II EDS)' then 'Cyclone V device support'.

After the files have been downloaded run the 'QuartusLiteSetup-16.0.0.211-windows.exe' file and as you progress through the setup it's best to keep with the default installation directory. When you get to the 'Select Components' page you should see that 'Cyclone V' is an option and has been checked (I downloaded the 'Cyclone V device support' file to the same directory as the main download file). Continue through the installation and when you get to the last page be sure to have the option checked to install the USB blaster II driver which will launch the driver installation wizard. After the driver has been installed and Quartus launches (assuming the option was checked to launch the software) a pop-up will appear for you to select a license option; just select 'Run the Quartus Prime software'. If the program doesn't actually launch then just run it from Windows (e.g. type 'Quartus' into the search bar). Note that I'm using 64-bit Windows 10 so I can confirm that Quartus 16.0 does run on Windows 10.

If you haven't already, download the user manual for your board revision from the following page:

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=836&PartNo=4

Also, in the 'CD-ROM' section of the page linked above click on the CD icon for your board revision, e.g. 'DE1-SoC CD-ROM (rev.F/rev.G Board)' and you will be taken to another page. Then click on the link for your board revision, e.g. 'DE1-SoC_v.5.1.3_HWrevF.revG_SystemCD.zip' and once downloaded extract it; if you get 'path too long' error copy the file you downloaded to a location closer to your drive (C: for most people) and try extracting again.

You will now have a number of folders as follows:

Datasheet - datasheets for the major components of the DE1-SoC board.

Demonstrations - within the subfolders are a number of Quartus example programs.

Schematic - a pdf of the circuit diagrams, unfortunately watermarked.

Tools - within the SystemBuilder folder is the System Builder utility which will be covered later.

UserManual - various guides and manuals.

As explained on page 60 of the user manual the DE1-SoC is pre-programmed with a default configuration as talked about at the start of the 'First steps' section of this page and the project files can be found in \Demonstrations\FPGA\DE1_SoC_Default.  To open a project in Quartus simply open the .qpf file using File->OpenProject... and the project will be loaded.

Now that Quartus has been downloaded you may be eager to program the DE1-SoC but it's a good idea to get the DE1-SoC System Builder which is a Windows-based utility that is designed to help users create a Quartus project for DE1-SoC within minutes as well as simplify the configuration of the DE1-SoC and reduce errors from bad designs.

The  System Builder can be downloaded from:

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=836&PartNo=4

Click on the CD icon to the right of 'DE1-SoC System Builder'.

The System Builder is also included with the 'CD-ROM' download as mentioned previously.

Once downloaded extract it and run the 'DE1SoC_SystemBuilder' file to launch the utility; there is no installation needed. You can see a screenshot of the utility below:

As listed on page 53 of the rev. f user manual the System Builder generates the following files.

• Quartus II project file (.qpf)

• Quartus II setting file (.qsf)

• Top-level design file (.v)

• Synopsis design constraints file (.sdc)

• Pin assignment document (.htm)

The two major files are the top-level design file (.v) and Quartus setting file (.qsf) with the top-level design file containing a top-level Verilog HDL wrapper for users to add their own

design/logic.

From page 54 the user manual explains how to use the System Builder but I will summarise here:

Enter the project name which will be assigned automatically as the name of the top-level design entity. 

Enable/disable components as needed. The System Builder will automatically generate an enabled component's associated pin assignment and I/O standard.

For Terasic GPIO-based daughter cards connected to the GPIO connectors the System Builder can generate a project that includes the corresponding modules and generate the associated pin assignment and I/O standard.

The System Builder also provides the option to load a setting or save the user's current board configuration in a .cfg file.

When the 'Generate' button is pressed the System Builder will generate the previously mentioned files (.v, .qpf, .qsf, .sdc, .htm) and save them followed by a pop-up telling you where the files have been saved.

You can then open up the project in Quartus and custom logic and code can then be added to the project as needed as with any standard Quartus project.

I attempted my own simple design by using the System Builder to generate the project files and I opened the project file in Quartus. I added a block diagram file (File->New... select Block Diagram/Schematic File and press OK) and created simple logic to turn LEDR0 on by connecting it to GND. I then compiled the project and connected power to the DE1-SoC board via the 12V socket and also connected the board to my PC using an A-B cable (the USB socket on the board is labelled as 'USB BLASTER II'). These are the steps I used to program the board:

Tools > Programmer: Hardware Setup... Select 'DE-SoC' in the drop-down of the currently selected hardware and click the close button; DE-SoC will now appear in the box next to the Hardware Setup... button.

The .sof file should be listed under file and make sure the Program/Configure box is checked. Click the Auto Detect button and in the pop-up window select '5CSEMA5' and click OK. You will then get a warning about the auto-detected device chain not matching the programmer's device list but click OK. Click 'Start' to program the board via JTAG. Note that powering off and back on will restore the previously saved configuration because we used JTAG to temporarily write the configuration, which is useful for quick testing.

You can read more about programming the DE1-SoC board in both JTAG and AS mode from page 14 of the user manual.

The I/O in more detail

ADC

The 8 analog inputs are available on the 2x5 'ADC CON' header as well as VCC5 (+5V) and GND with the pinout listed on page 42 of the user manual. Note the square outline in the pinout diagram denoting pin 1, this is duplicated on the actual PCB on the back. Turns out that when viewing the PCB from the front the right way up pin 1 of the ADC connector is diagonally opposite to what the diagram in the manual shows. So the top-left hand pin is actually pin 10, GND.

GPIO expansion headers

Each of the two GPIO expansion headers consists of 20x2 pins and provide 36 I/O as well as VCC5 (+5V), VCC3P3 (+3.3V) and two GND connections. Although the user manual lists the GPIO expansion header signal names with their descriptions and I/O standard no actual pinout is given. While the System Builder application shows the GPIO pinout as a diagram when 'GPIO Default' is chosen (which is what you should select for general purpose I/O) for either expansion header it's too small to see, at least on my PC. However, the schematic (found in the Schematic folder of the 'CD' download) shows the pinout which I have repeated here:

Pin one is top left of the connector and the pinout for GPIO 0 is as follows with the signal names you need to use in your design:

1 GPIO_0[0] 2 GPIO_0[1]

3 GPIO_0[2] 4 GPIO_0[3]

5 GPIO_0[4] 6 GPIO_0[5]

7 GPIO_0[6] 8 GPIO_0[7]

9 GPIO_0[8] 10 GPIO_0[9]

11 VCC5 12 GND

13 GPIO_0[10] 14 GPIO_0[11]

15 GPIO_0[12] 16 GPIO_0[13]

17 GPIO_0[14] 18 GPIO_0[15]

19 GPIO_0[16] 20 GPIO_0[17]

21 GPIO_0[18] 22 GPIO_0[19]

23 GPIO_0[20] 24 GPIO_0[21]

25 GPIO_0[22] 26 GPIO_0[23]

27 GPIO_0[24] 28 GPIO_0[25]

29 VCC3P3 30 GND

31 GPIO_0[26] 32 GPIO_0[27]

33 GPIO_0[28] 34 GPIO_0[29]

35 GPIO_0[30] 36 GPIO_0[31]

37 GPIO_0[32] 38 GPIO_0[33]

39 GPIO_0[34] 40 GPIO_0[35]

The pinout for GPIO 1 is the same as above but with the signal names appropriate for GPIO 1 (GPIO_1[0], GPIO_1[1], etc.).

VGA

The DE1-SoC can generate video resolutions from 640x480 @ 60Hz (VGA) and up to 1280x1024 @ 60Hz (SXGA); see page 34 of the user manual for a complete list of resolutions and associated timing. On then end of page 32 of the user manual it explains how the board handles VGA and page 33 shows an illustration of how the VGA signals are routed to the VGA connector. In summary:

VGA_R[7..0], VGA_G[7..0], VGA_B[7..0], VGA_CLK, VGA_SYNC_N and VGA_BLANK_N are connected to the VGA DAC which produces the RGB analog signals present on the VGA connector.

The other two signals, VGA_VS and VGA_HS are also generated from the FPGA but are routed directly to the VGA connector.

VGA_BLANK_N when taken low turns off the RGB outputs (which should be done during the video blank period) and VGA_SYNC_N is used for handling sync on green (if not used, ensure VGA_SYNC_N is held low).

Please see this site for an introduction into generating VGA timing using VHDL:

https://www.digikey.com/eewiki/pages/viewpage.action?pageId=15925278 

Resources

Introduction to Cyclone V Hard Processor System:

https://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/HPS_INTRO_54001.pdf

Please see my introduction to FPGAs at:

https://sites.google.com/site/jamesskingdom/Home/electronics-by-james-s/digital-electronics-by-james-s/field-programmable-gate-array

You may also be interested in the Cyclone II board I've reviewed which you can find at:

https://sites.google.com/site/jamesskingdom/Home/electronics-by-james-s/digital-electronics-by-james-s/field-programmable-gate-array#h.p_ID_109

All content of this and related pages is copyright (c) James S. 2020