Jiho Han
Department of Electronic Engineering, Sun Moon University
College of Engineering 610B, 70, Sunmoon-ro 221, Tangjeong, Asan, Chungnam, Korea 31460
jihohanATsunmoonDOTacDOTkr
Education
2009 PhD in Electrical Engineering and Computer Science, Seoul National University
Dissertation : A High-Accuracy Clock Synchronization System over Packet Switched Networks
Advisor : Prof. Deog-Kyoon Jeong
2004 MS in Electrical Engineering and Computer Science, Seoul National University
2002 BS in Electrical Engineering, Seoul National University, Korea
Publications, Journal
Jiho Han, “White Rabbit Clock Synchronization with 100-ps Accuracy for Wireless TSN over WiFi Networks,” Advances in Electrical and Computer Engineering, vol. x, no. x, pp. 1-8, 2025. (under review)
Jiho Han, “The Evolution of Bitcoin Hardware,” Journal of Next-Generation Convergence Technology, vol. x, no. x, pp. 1-6, 2025. (under review)
Changyong Shin and Jiho Han, “Non-Orthogonal Multiple Access Enhancing Spectral Efficiency for Multi-Cell Systems,” Journal of Institute of Korean Electrical and Electronics Engineers, vol. 29, no. 1, pp. 49-57, Mar. 2025.
Jiho Han and Changyong Shin, “Clock Synchronization Technologies and Protocols for Wireless Time-Sensitive Networking,” Journal of Next-Generation Convergence Technology, vol. 9, no. 3, pp. 633-642, Mar. 2025.
Jiho Han and Changyong Shin, “An Extensive PUF of Bistable Rings Feed-Forward Chains with Lightweight Secure Architecture for Enhanced ML Attack Resistance,” Journal of Semiconductor Technology and Science, vol. 24, no. 2, pp. 76-83, Apr. 2024.
Jiho Han and Changyong Shin, “Practical Implementation of Strong Physical Unclonable Functions as Hardware Security for Internet of Things,” Journal of Next-Generation Convergence Technology, vol. 7, no. 8, pp. 1173-1181, Aug. 2023.
Changyong Shin and Jiho Han, “Multi-cell Interference Mitigation for MIMO Non-orthogonal Multiple Access Systems,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E104-A, no. 5, pp. 838-843, May 2021.
Jiho Han and Changyong Shin, “A Circuit Implementation of 1000BASE-T White Rabbit using MMCMs and SyncE Frequency Transfer for High-Accuracy Clock Synchronization,” Journal of Semiconductor Technology and Science, vol. 20, no. 4, pp. 320-325, Aug. 2020.
Changyong Shin and Jiho Han, “Digital Self-Interference Cancellation for LTE-Compatible In-Band Full-Duplex Systems,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E101-A, no. 5, pp. 1-6, May 2018.
KiBeom Ham, Jiho Han, and YongJai Park, “Soft Gripper using Variable Stiffness Mechanism and Its Application,” International Journal of Precision Engineering and Manufacturing, vol. 19, No. 4, pp. 487-494, Apr. 2018.
Jiho Han and Changyong Shin, “A Nanosecond-Accuracy Clock Synchronization Circuit for IEEE 1588-2008 Using Tapped Delay Lines,” IEICE Electronics Express, vol. 13, no. 23, pp. 1-6, Dec. 2016.
KiBeom Ham, Jiho Han, JongKyun Jeon, and YongJai Park, “Parametric Study on the tendency of Stiffness Variation using Variable Stiffness Mechanism,” Journal of the Korea Academia-Industrial cooperation Society, vol. 17, no. 6, pp. 750-758, Jul. 2016.
Jiho Han and Yong-Jai Park, “Design of a IEEE 1588 Based Clock Synchronization System for Femtocell Frequency Signal Generation,” Journal of the Korea Academia-Industrial cooperation Society, vol. 16, no. 7, pp. 4871-4877, Jul. 2015.
Byung-Joo Yoo, Woo-Rham Bae, Jiho Han, Jaeha Kim, and Deog-Kyoon Jeong, “Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 6, pp. 1226-1237, Jun. 2014.
Jiho Han and Deog-Kyoon Jeong, “A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems,” IEEE Transactions on Instrumentation and Measurement, vol. 59, no. 2, pp. 433-439, Feb. 2010.
Jiho Han and Deog-Kyoon Jeong, “Practical Considerations in the Design and Implementation of Time Synchronization Systems Using IEEE 1588,” IEEE Communications Magazine, vol. 47, no. 11, pp. 164-170, Nov. 2009.
Jonghoon Lee, Chul-Ki Lee, Jiho Han, Hankyu Chi, Taesik Na, Deog-Kyoon Jeong, Jaehwa Kwak, Jin-su Ahn, and Sangho Yoon, “An Ethernet Switch Architecture for Bandwidth Provision of Broadband Access Networks,” IEEE Communications Magazine, vol. 46, no. 4, pp. 160-167, Apr. 2008.
Han-Kyu Lim, Jiho Han, and Deog-Kyoon Jeong, “A Network Storage LSI Suitable for Home Network,” Journal of Semiconductor Technology and Science, vol. 4, no. 4, pp. 258-262, Dec. 2004.
Work Experience
2014-Present Department of Electronic Engineering, Sun Moon University
Associate Professor
2021-2022 Electrical and Computer Engineering, Texas A&M University
Visiting Scholar
2017-2020 A High-Accuracy Clock Synchronization System over Packet Switched Networks with National Research Foundation of Korea
Implement White Rabbit devices using Unshielded twisted pair (UTP) cables.
Analyze and eliminate the sources of synchronization error by applying Kalman filters and tapped delay lines.
2009-2014 Smart Card, System LSI, Samsung Electronics
Designed RFID and SIM chips containing a microprocessor core, embedded flash memories, encryption and security IPs, and communication circuits.
Experienced state-of-the-art SoC design methodologies and EDA tools for full-chip integration, physical implementation, DFT, and failure analysis.
Proposed a new RF demodulation logic for the next-generation contactless communication up to 6.8 Mbps.
2006-2008 IEEE 1588-compliant NIC working over a network based on non-AVB Ethernet switches with Samsung Advanced Institute of Technology (SAIT)
Designed a network adapter supporting IEEE 1588-2008 for the clock synchronization of telecom base stations.
Implemented prototypes using FPGA devices to analyze the synchronization performance over the realistic network.
2005-2006 The platform implementation of a multi-service switch device with Electronics and Telecommunications Research Institute (ETRI)
Implemented a multi-service switch chip for Broadband convergence network (BcN) reusing the existing IPs.
Verified the system functions and timing by post-layout gate-level simulation.
2003-2005 A System-on-a-Chip for the next-generation network equipment with Ministry of Trade, Industry & Energy
Implemented a carrier-grade multi-layer gigabit Ethernet switch supporting L3/L4/L7 protocols.
Designed 10/100/1000 Mbps MAC core, link status control, and MII-to-GMII conversion circuit.
Invented a dedicated elastic buffer to solve the clock domain crossing (CDC) problem.
Set up an FPGA-based emulation environment running at the 1/10 speed.
2004 10/100/100 Mbps Ethernet Media access control (MAC) IP with Electronics and Telecommunications Research Institute (ETRI)
Developed a synthesizable MAC IP optimized for gigabit Ethernet SoCs.
Analyzed the existing IPs of semiconductor companies and open cores. Introduced a new verification procedure for interoperability.
2002-2003 1000BASE-T / 1000BASE-X network adapter with Glonet Systems
Implemented 10/100/1000 Mbps Ethernet MAC for Gigabit Ethernet network adapter.
Designed a packet buffer working as a priority queue based on IEEE 802.1p to support Quality of service (QoS)
