Embedded Files
Officail Website Reference:
Officail Website Reference:
The customizable Integrated Logic Analyzer (ILA) IP core is a logic analyzer core that can be used to monitor the internal signals of a design. The ILA core includes many advanced features of modern logic analyzers, including Boolean trigger equations, and edge transition triggers. Because the ILA core is synchronous to the design being monitored, all design clock constraints that are applied to your design are also applied to the components inside the ILA core.
Inline Logic Analyzer Measurement Flow
Mark debug tags on the desired registers in your design.
Synthesize your design and wait for Vivado to automatically insert the Integrated Logic Analyzer (ILA) IP into your design.
Generate the bitstream file and upload it to the FPGA board.
Manipulate the ILA windows to monitor and analyze the data from the tagged registers.
RTL Example (Note: debug tag)
RTL Example (Note: debug tag)
Run "Synthesis"
Run "Synthesis"
After sythesized, open "Set Up Debug"
After sythesized, open "Set Up Debug"
Ensure that the debug setup wizard has selected the correct signals, and keep the other configurations at their default settings. Don't forget ctrl+s to save the file.
Ensure that the debug setup wizard has selected the correct signals, and keep the other configurations at their default settings. Don't forget ctrl+s to save the file.
Generate the bitstream and upload all files to the FPGA board. The ILA windows will launch automatically.
Generate the bitstream and upload all files to the FPGA board. The ILA windows will launch automatically.
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